How to Dynamically Switch Between Serial and Parallel Modes Using ISO1228
Abstract
Further information on device operation is available in the ISO1228 Eight-Channel Isolated Digital Input with Current Limit and Diagnostics, data sheet and ISO1228DFBEVM EVM. This guide is used to explain the performance benefits of serial and parallel mode and how to switch dynamically between modes for the best functionality.
24V digital input systems have a growing need to support higher channel density and to integrate various features (Space-Saving Design Techniques for Multichannel High- Voltage Digital Input Modules). The ISO1228 address both needs as an eight-channel isolated 24V digital input receiver that can use a serial (SPI) or a parallel digital output mode to control various integrated digital features such as: wire-break detection, in-built glitch filters, field-side supply monitoring and built-in CRC across the isolation barrier. Additionally, designers can use the serial mode to monitor the inputs over SPI and reduce the number of pins in an MCU. The isolated logic side can range from 1.71V to 5.5V, supporting 1.8V, 2.5V, 3.3V, and 5V controllers. The field side supply voltage can range from 8.5V to 36V in sink mode and 13V to 36V in source mode. ISO1228 supports data rates up to 1.5Mbps, and can pass a minimum pulse width of 667ns for high-speed operation.
The ISO1228 is designed to comply with the IEC 61131-2 standard for digital inputs and supports eight channels with IEC 61131-2 Type 1, and 3 characteristics or four channels with Type 2 characteristics. The ISO1228 also includes integrated resistor-programmable current limiting and field side, input-current-powered LED indication to reduce the system's power dissipation and board temperature. ISO1228 can be configured for either sourcing or sinking type digital inputs with minimal hardware changes. The ISO1228 also supports IEC ESD and surge protection to achieve a robust design.
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1 ISO1228 - Relevant Device Information
The following ISO1228 data sheet tables and pinout are provided for reference.
Figure 1-1 ISO1228 Pinout| PIN | I/O | Description | |
|---|---|---|---|
| NO. | NAME | ||
| 1 | IN1 | I/O | Field Input, Channel 1 |
| 2 | LED1 | I/O | LED Indication Pin, Channel 1 |
| 3 | IN2 | I/O | Field Input, Channel 2 |
| 4 | LED2 | I/O | LED Indication Pin, Channel 2 |
| 5 | IN3 | I/O | Field Input, Channel 3 |
| 6 | LED3 | I/O | LED Indication Pin, Channel 3 |
| 7 | AVSS | — | Field Side Negative Supply |
| 8 | IN4 | I/O | Field Input, Channel 4 |
| 9 | LED4 | I/O | LED Indication Pin, Channel 4 |
| 10 | IN5 | I/O | Field Input, Channel 5 |
| 11 | LED5 | I/O | LED Indication Pin, Channel 5 |
| 12 | IN6 | I/O | Field Input, Channel 6 |
| 13 | LED6 | I/O | LED Indication Pin, Channel 6 |
| 14 | IN7 | I/O | Field Input, Channel 7 |
| 15 | LED7 | I/O | LED Indication Pin, Channel 7 |
| 16 | AVCC | — | Field Side Power Supply |
| 17 | AVSS | — | Field Side Negative Supply |
| 18 | IN8 | I/O | Field Input, Channel 8 |
| 19 | LED8 | I/O | LED Indication Pin, Channel 8 |
| 20 | NC | — | Leave unconnected |
| 21 | GND1 | — | Logic Ground |
| 22 | NC | — | Leave unconnected |
| 23 | F1 | I | Digital Filter Setting |
| 24 | F0 | I | Digital Filter Setting |
| 25 | GND1 | — | Logic Ground |
| 26 | nFAULT | O | Open Drain Ouput. Connect 4.7 kΩ pull-up to VCC1 |
| 27 | OUT_EN | I | Ouput Enable. Output pins OUT1 through OUT8 are tri-stated if OUT_EN=0 or FLOAT |
| 28 | OUT8/SYNC | O | Synchronize data in Burst
Mode(COMM_SEL=VCC1) Data Output, Channel 8, in Parallel Interface Mode (COMM_SEL=0) |
| 29 | OUT7/BURST_EN | I/O | Burst Mode in Serial
Interface Mode (COMM_SEL=VCC1) Data Output, Channel 7, in Parallel Interface Mode (COMM_SEL=0) |
| 30 | OUT6/nRST | I/O | Active Low SPI Reset in
Serial Interface Mode (COMM_SEL=VCC1) Data Output, Channel 6, in Parallel Interface Mode (COMM_SEL=0) |
| 31 | OUT5/nINT | O | Active Low SPI Interrupt in
Serial Interface Mode (COMM_SEL=VCC1) Data Output, Channel 5, in Parallel Interface Mode (COMM_SEL=0) |
| 32 | OUT4/nCS | I/O | SPI Chip Seltect in Serial
Interface Mode (COMM_SEL=VCC1) Data Output, Channel 4, in Parallel Interface Mode (COMM_SEL=0) |
| 33 | OUT3/SCLK | I/O | SPI Clock in Serial
Interface Mode (COMM_SEL=VCC1) Data Output, Channel 3, in Parallel Interface Mode (COMM_SEL=0) |
| 34 | OUT2/SDI | I/O | SPI Input Data in Serial
Interface Mode (COMM_SEL=VCC1) Data Output, Channel 2, in Parallel Interface Mode (COMM_SEL=0) |
| 35 | OUT1/SDO | O | SPI Output Data in Serial
Interface Mode (COMM_SEL=VCC1) Data Output, Channel 1, in Parallel Interface Mode (COMM_SEL=0) |
| 36 | GND1 | — | Logic Ground |
| 37 | VCC1 | — | Logic Supply |
| 38 | COMM_SEL | I | Serial vs. Parallel
Interface selection Serial Interface Mode if COMM_SEL=VCC1 Parallel Interface Mode if COMM_SEL=0 or Floating |
| Address | NAME | R/W | DESCRIPTION |
|---|---|---|---|
| 00h | Input Data | R |
Data Information: <7> = IN8 <6> = IN7 . . <0> = IN1 |
| 01h | Wire Break | R |
Wire Break Information: <7> = WB8 <6> = WB7 <5> = WB6 . . <0> = WB1 |
| 02h | Fault | R |
Provides the details of the faults in the design: <7> = WB (Any channel shows WB) <6> = OT (Over-temperature threshold is crossed) <5> = Reserved <4> = CRC (Inter-die CRC is in error) <3> = Reserved <2> = Field Side Power Loss <1> = Reserved <0> = UVLO (MCU Side) |
| 03h | Filter Ch 1 and Ch 2 | R/W | <7> = Filt Enable, Ch 1 <6:4> = Filter Settings, Ch 1 <3> = Filt Enable, Ch 2<2:0> = Filter Settings, Ch 2 |
| 04h | Filter Ch 3 and Ch 4 | R/W | <7> = Filt Enable, Ch 3 <6:4> = Filter Settings, Ch 3 <3> = Filt Enable, Ch 4<2:0> = Filter Settings, Ch 4 |
| 05h | Filter Ch 5 and Ch 6 | R/W | <7> = Filt Enable, Ch 5 <6:4> = Filter Settings, Ch 5 <3> = Filt Enable, Ch 6<2:0> = Filter Settings, Ch 6 |
| 06h | Filter Ch 7 and Ch 8 | R/W | <7> = Filt Enable, Ch 7 <6:4> = Filter Settings, Ch 7 <3> = Filt Enable, Ch 8<2:0> = Filter Settings, Ch 8 |