ADS130B02-Q1Functional Safety FIT Rate, FMD and Pin FMA

Trademarks

All trademarks are the property of their respective owners.

1 Overview

This document contains information for the ADS130B02-Q1 (TSSOP package) to aid in a functional safety system design. Information provided are:

Functional safety failure in time (FIT) rates of the semiconductor component estimated by the application of industry reliability standards
Pin failure mode analysis (pin FMA)

Figure 1-1 shows the device functional block diagram for reference.

Figure 1-1 Functional Block Diagram

The ADS130B02-Q1 was developed using a quality-managed development process, but was not developed in accordance with the IEC 61508 or ISO 26262 standards.

2 Functional Safety Failure In Time (FIT) Rates

This section provides functional safety failure in time (FIT) rates for the ADS130B02-Q1 based on two different industry-wide used reliability standards:

Table 2-1 provides FIT rates based on IEC TR 62380 / ISO 26262 part 11
Table 2-2 provides FIT rates based on the Siemens Norm SN 29500-2

Table 2-1 Component Failure Rates per IEC TR 62380 / ISO 26262 Part 11

FIT IEC TR 62380 / ISO 26262	FIT (Failures Per 10⁹ Hours)
Total component FIT rate	13
Die FIT rate	2
Package FIT rate	11

The failure rate and mission profile information in Table 2-1 comes from the reliability data handbook IEC TR 62380 / ISO 26262 part 11:

Mission profile: Motor control from table 11
Power dissipation: 15.2 mW
Climate type: World-wide table 8
Package factor (lambda 3): Table 17b
Substrate material: FR4
EOS FIT rate assumed: 0 FIT

Table 2-2 Component Failure Rates per Siemens Norm SN 29500-2

Table	Category	Reference FIT Rate	Reference Virtual T_J
5	CMOS, BICMOS Digital, analog, or mixed	60 FIT	70°C

The reference FIT rate and reference virtual T_J (junction temperature) in Table 2-2 come from the Siemens Norm SN 29500-2 tables 1 through 5. Failure rates under operating conditions are calculated from the reference failure rate and virtual junction temperature using conversion information in SN 29500-2 section 4.

3 Failure Mode Distribution (FMD)

The failure mode distribution estimation for the ADS130B02-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.

The failure modes listed in this section reflect random failure events and do not include failures resulting from misuse or overstress.

Table 3-1 Die Failure Modes and Distribution

Die Failure Modes	Failure Mode Distribution (%)
Incorrect conversion result of individual ADC⁽¹⁾. (For example, ADC output code at positive or negative full scale, at 0 V, undetermined or otherwise incorrect.)	25%
SPI communication error	15%
Register bit error leading to incorrect device configuration. (Device behavior depends on which user or internal register bit is affected.)	15%
Gain error of individual ADC out of specification⁽¹⁾	10%
Offset error of individual ADC out of specification⁽¹⁾	5%
Noise of conversion result of individual ADC out of specification⁽¹⁾	5%
INL of individual ADC out of specification⁽¹⁾	5%
Gain error, INL, or noise of conversion results of both ADCs out of specification resulting from common circuitry. (Common circuitry includes internal supplies, voltage reference, bias current generator, and clock.)	5%
Oscillator fault leading to incorrect data rate. (For example, oscillator frequency too high or low, oscillator output stuck-at.)	5%
ADC output code bit stuck-at	5%
Device behavior undetermined	5%

(1) The failure mode percentage provided is for the sum of the two ADCs. For a single ADC divide the failure mode percentage by 2x.