SCAA124 April   2015 RM41L232 , RM42L432 , RM44L520 , RM44L920 , RM46L430 , RM46L440 , RM46L450 , RM46L830 , RM46L840 , RM46L850 , RM46L852 , RM48L530 , RM48L540 , RM48L730 , RM48L740 , RM48L940 , RM48L950 , RM48L952 , RM57L843 , TMS570LC4357 , TMS570LC4357-EP , TMS570LC4357-SEP , TMS570LS0232 , TMS570LS0332 , TMS570LS0432 , TMS570LS0714 , TMS570LS0714-S , TMS570LS0914 , TMS570LS1114 , TMS570LS1115 , TMS570LS1224 , TMS570LS1225 , TMS570LS1227 , TMS570LS2124 , TMS570LS2125 , TMS570LS2134 , TMS570LS2135 , TMS570LS2135-S , TMS570LS3134 , TMS570LS3135 , TMS570LS3137

 

  1.   Latch-Up
    1.     Trademarks
    2. 1 Introduction
      1. 1.1 What is Latch-Up?
      2. 1.2 Latch-Up Model
      3. 1.3 Mitigating Latch-Up
    3. 2 Latch-Up Testing Methods
      1. 2.1 Latch-Up Standard
      2. 2.2 Current Injection Stress
      3. 2.3 Over-Voltage Stress
      4. 2.4 Signal Latch-Up
      5. 2.5 Analog Product Testing
        1. 2.5.1 Maximum Stress Voltage for Latch-Up (MSV)
        2. 2.5.2 Stressing Special Pins
        3. 2.5.3 High Voltage Testing
    4. 3 References

Latch-Up

This document describes and discusses the topic of CMOS Latch-Up ranging from theory to testing of products. The recently proposed modifications to JEDEC standard JESD78 are discussed along with progress for making it more analog friendly with respect to special pin functions and/or high voltage requirements.