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This document describes and discusses the topic of CMOS Latch-Up ranging from theory to testing of products. The recently proposed modifications to JEDEC standard JESD78 are discussed along with progress for making it more analog friendly with respect to special pin functions and/or high voltage requirements.
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Latch-Up today is still a potentially potent source of failure in the qualification flow at manufacturers and in the customer application. As IC’s get smaller, so do the dimensions between transistors within an IC. Transistor spacing can create conditions for Latch-Up. Texas Instruments is influencing the industry to consider more complete methods to stress Latch-Up in all products but in particular, analog products. The goal at Texas Instruments is to continuously improve the quality and reliability of the products.