TPS7A85 High-Current (4 A), High-Accuracy (1%), Low-Noise (4.4 µVRMS), LDO Voltage Regulator
- SBVS267A January 2016 – February 2016 TPS7A85
  
  PRODUCTION DATA.

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DATA SHEET

TPS7A85 High-Current (4 A), High-Accuracy (1%), Low-Noise (4.4 µVRMS), LDO Voltage Regulator

1 Features

Low Dropout: 150 mV (typ) at 4 A
1% (max) Accuracy Over Line, Load, and Temperature
Output Voltage Noise:
- 4.4 µV_RMS at 0.8-V Output
- 8.4 µV_RMS at 5.0-V Output
Input Voltage Range:
- Without BIAS: 1.4 V to 6.5 V
- With BIAS: 1.1 V to 6.5 V
ANY-OUT™ Operation:
- Output Voltage Range: 0.8 V to 3.95 V
Adjustable Operation:
- Output Voltage Range: 0.8 V to 5.0 V
Power-Supply Ripple Rejection:
- 40 dB at 500 kHz
Excellent Load Transient Response
Adjustable Soft-Start In-Rush Control
Open-Drain Power-Good (PG) Output
Stable with a 47-µF or Larger Ceramic Output Capacitor
Operating Temperature Range:
–40ºC to +125°C
3.5-mm × 3.5-mm, 20-Pin VQFN

2 Applications

Digital Loads: SerDes, FPGAs, and DSPs
Instrumentation, Medical, and Audio
High-Speed Analog Circuits:
- VCO, ADC, DAC, and LVDS
Imaging: CMOS Sensors and Video ASICs
Test and Measurement

3 Description

The TPS7A85 is a low-noise (4.4 µV_RMS), low-dropout linear regulator (LDO) capable of sourcing 4 A with only 240 mV of maximum dropout. The device output voltage is pin-programmable from 0.8 V to 3.95 V and adjustable from 0.8 V to 5.0 V using an external resistor divider.

The combination of low-noise (4.4 µV_RMS), high-PSRR, and high output current capability makes the TPS7A85 ideal to power noise-sensitive components such as those found in high-speed communications, video, medical, or test and measurement applications. The high performance of the TPS7A85 limits power-supply-generated phase noise and clock jitter, making this device ideal for powering high-performance serializer and deserializer (SerDes), analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and RF components. Specifically, RF amplifiers benefit from the high-performance and 5.0-V output capability of the device.

For digital loads [such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and digital signal processors (DSPs)] requiring low-input voltage, low-output (LILO) voltage operation, the exceptional accuracy (0.75% over load and temperature), remote sensing, excellent transient performance, and soft-start capabilities of the TPS7A85 ensure optimal system performance.

The versatility of the TPS7A85 makes the device a component of choice for many demanding applications.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (nom)
TPS7A85	VQFN (20)	3.50 mm × 3.50 mm

For all available packages, see the orderable addendum at the end of the datasheet.

Powering RF Components

Powering Digital Loads

4 Revision History

Changes from * Revision (January 2016) to A Revision

Released to production Go

5 Pin Configurations and Functions

RGR Package

3.5-mm × 3.5-mm, 20-Pin VQFN

Top View

Pin Functions

PIN			DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
50mV	5	I	ANY-OUT voltage setting pins. Connect these pins to ground, SNS, or leave floating. Connecting these pins to ground increases the output voltage, whereas connecting these pins to SNS increases the resolution of the ANY-OUT network but decreases the range of the network; multiple pins can be simultaneously connected to GND or SNS to select the desired output voltage. Leave these pins floating (open) when not in use. See the ANY-OUT Programmable Output Voltage section for additional details.
100mV	6
200mV	7
400mV	9
800mV	10
1.6V	11
BIAS	12	I	BIAS supply voltage. This pin enables the use of low-input voltage, low-output (LILO) voltage conditions (that is, V_IN = 1.2 V, V_OUT = 1 V) to reduce power dissipation across the die. The use of a BIAS voltage improves dc and ac performance for V_IN ≤ 2.2 V. A 10-µF capacitor or larger must be connected between this pin and ground. If not used, this pin must be left floating or tied to ground.
EN	14	I	Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low disables the device. If enable functionality is not required, this pin must be connected to IN. If enable functionality is required, V_EN must always be high after V_IN is established when a BIAS supply is used. See the Sequencing Requirements section for more details.
FB	3	I	Feedback pin connected to the error amplifier. Although not required, a 10-nF feed-forward capacitor from FB to OUT (as close to the device as possible) is recommended to maximize ac performance. The use of a feed-forward capacitor can disrupt PG (power good) functionality. See the ANY-OUT Programmable Output Voltage and Adjustable Operation sections for more details.
GND	8, 18	—	Ground pin. These pins must be connected to ground, the thermal pad, and each other with a low-impedance connection.
IN	15-17	I	Input supply voltage pins. A 47-μF or larger ceramic capacitor (25 μF or greater of effective capacitance) from IN to ground is recommended to reduce the impedance of the input supply. Place the input capacitor as close to the input as possible. See the Input and Output Capacitor Requirements section for more details.
NR/SS	13	—	Noise-reduction and soft-start pin. Connecting an external capacitor between this pin and ground reduces reference voltage noise and also enables the soft-start function. Although not required, a 10-nF or larger capacitor is recommended to be connected from NR/SS to GND (as close to the pin as possible) to maximize ac performance. See the Noise-Reduction and Soft-Start Capacitor section for more details.
OUT	1, 19, 20	O	Regulated output pins. A 47-μF or larger ceramic capacitor (25 μF or greater of effective capacitance) from OUT to ground is required for stability and must be placed as close to the output as possible. Minimize the impedance from the OUT pin to the load. See the Input and Output Capacitor Requirements section for more details.
PG	4	O	Active-high, power-good pin. An open-drain output indicates when the output voltage reaches 89.3% of the target. The use of a feed-forward capacitor can disrupt PG (power good) functionality. See the Power-Good (PG) Function section for more details.
SNS	2	I	Output voltage sense input pin. This pin connects the internal R₁ resistor to the output. Connect this pin to the load side of the output trace only if the ANY-OUT feature is used. If the ANY-OUT feature is not used, leave this pin floating. See the ANY-OUT Programmable Output Voltage and Adjustable Operation sections for more details.
Thermal pad		—	Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.

6 Specifications

6.1 Absolute Maximum Ratings

over junction temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Voltage	IN, BIAS, PG, EN	–0.3	7.0	V
	IN, BIAS, PG, EN (5% duty cycle, pulse duration = 200 µs)	–0.3	7.5
	SNS, OUT	–0.3	V_IN + 0.3⁽²⁾
	NR/SS, FB	–0.3	3.6
	50mV, 100mV, 200mV, 400mV, 800mV, 1.6V	–0.3	V_OUT + 0.3
Current	OUT	Internally limited		A
Current	PG (sink current into device)		5	mA
Operating junction temperature, T_J		–55	150	°C
Storage temperature, T_stg		–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The absolute maximum rating is V_IN + 0.3 V or 7.0 V, whichever is smaller.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over junction temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
V_IN	Input supply voltage range	1.1		6.5	V
V_BIAS	Bias supply voltage range⁽¹⁾	3.0		6.5	V
V_OUT	Output voltage range⁽²⁾	0.8		5	V
V_EN	Enable voltage range	0		V_IN	V
I_OUT	Output current	0		4	A
C_IN	Input capacitor	10	47		µF
C_OUT	Output capacitor	47	47 \|\| 10 \|\| 10⁽³⁾		µF
R_PG	Power-good pullup resistance	10		100	kΩ
C_NR/SS	NR/SS capacitor		10		nF
C_FF	Feed-forward capacitor		10		nF
R₁	Top resistor value in feedback network for adjustable operation		12.1⁽⁴⁾		kΩ
R₂	Bottom resistor value in feedback network for adjustable operation			160⁽⁵⁾	kΩ
T_J	Operating junction temperature	–40		125	°C

(1) BIAS supply is required when the V_IN supply is below 1.4 V. Conversely, no BIAS supply is required when the V_IN supply is higher than or equal to 1.4 V. A BIAS supply helps improve dc and ac performance for V_IN ≤ 2.2 V.

(2) This output voltage range does not include device accuracy or accuracy of the feedback resistors.

(3) The recommended output capacitors are selected to optimize PSRR for the frequency range of 400 kHz to 700 kHz. This frequency range is a typical value for dc-dc supplies.

(4) The 12.1-kΩ resistor is selected to optimize PSRR and noise by matching the internal R₁ value.

(5) The upper limit for the R₂ resistor is to ensure accuracy by making the current through the feedback network much larger than the leakage current into the feedback node.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS7A85	UNIT
		RGR (VQFN)
		20 PINS
R_θJA	Junction-to-ambient thermal resistance	35.4	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	47.6	°C/W
R_θJB	Junction-to-board thermal resistance	12.3	°C/W
ψ_JT	Junction-to-top characterization parameter	0.5	°C/W
ψ_JB	Junction-to-board characterization parameter	12.4	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	1.0	°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Over operating junction temperature range (T_J = –40°C to +125°C), V_IN = 1.4 V or V_IN = V_OUT(nom) + 0.5 V (whichever is greater), V_BIAS = open, V_OUT(nom) = 0.8 V⁽²⁾, OUT connected to 50 Ω to GND⁽³⁾, V_EN = 1.1 V, C_IN = 10 μF, C_OUT = 47 μF, C_NR/SS without C_FF, and PG pin pulled up to V_IN with 100 kΩ, unless otherwise noted. Typical values are at T_J = 25°C.

PARAMETER			TEST CONDITIONS		MIN	TYP	MAX	UNIT
V_IN	Input supply voltage range⁽¹⁾				1.1		6.5	V
V_BIAS	Bias supply voltage range⁽¹⁾		V_IN= 1.1 V		3.0		6.5	V
V_FB	Feedback voltage					0.8		V
V_NR/SS	NR/SS pin voltage					0.8		V
V_UVLO1(IN)	Input supply UVLO with BIAS		V_IN rising with V_BIAS = 3.0 V			1.02	1.085	V
V_HYS1(IN)	V_UVLO1(IN) hysteresis		V_BIAS = 3.0 V			320		mV
V_UVLO2(IN)	Input supply UVLO without BIAS		V_IN rising			1.31	1.39	V
V_HYS2(IN)	V_UVLO2(IN) hysteresis					253		mV
V_UVLO(BIAS)	Bias supply UVLO		V_BIAS rising, V_IN = 1.1 V			2.83	2.9	V
V_HYS(BIAS)	V_UVLO(BIAS) hysteresis		V_IN = 1.1 V			290		mV
V_OUT	Output voltage	Range	Using the ANY-OUT pins		0.8 – 1.0%		3.95 + 1.0%	V
		Range	Using external resistors⁽⁴⁾		0.8 – 1.0%		5.0 + 1.0%	V
		Accuracy⁽⁴⁾⁽⁵⁾	0.8 V ≤ V_OUT ≤ 5 V, 5 mA ≤ I_OUT ≤ 4 A, over V_IN		–1.0%		1.0%
		Accuracy with BIAS	V_IN = 1.1 V, 5 mA ≤ I_OUT ≤ 4 A, 3.0 V ≤ V_BIAS ≤ 6.5 V		–0.75%		0.75%
ΔV_OUT/ ΔV_IN	Line regulation		I_OUT = 5 mA, 1.4 V ≤ V_IN ≤ 6.5 V			0.0035		mV/V
ΔV_OUT/ ΔI_OUT	Load regulation		5 mA ≤ I_OUT ≤ 4 A, 3.0 V ≤ V_BIAS ≤ 6.5 V, V_IN= 1.1 V			0.07		mV/A
			5 mA ≤ I_OUT ≤ 4 A			0.08
			5 mA ≤ I_OUT ≤ 4 A, V_OUT = 5.0 V			0.4
V_DO	Dropout voltage		V_IN = 1.4 V, I_OUT = 4 A, V_FB = 0.8 V – 3%			215	320	mV
			V_IN = 5.5 V, I_OUT = 4 A, V_FB = 0.8 V – 3%			325	500
			V_IN = 1.1 V, V_BIAS = 5.0 V, I_OUT = 4 A, V_FB = 0.8 V – 3%			150	240
I_LIM	Output current limit		V_OUT forced at 0.9 × V_OUT(nom), V_IN = V_OUT(nom) + 0.4 V		4.7	5.2	5.7	A
I_SC	Short-circuit current limit		R_LOAD = 20 mΩ			1.0		A
I_GND	GND pin current		V_IN = 6.5 V, I_OUT = 5 mA			2.8	4.0	mA
			V_IN = 1.4 V, I_OUT = 4 A			4.8	6.0	mA
			Shutdown, PG = open, V_IN = 6.5 V, V_EN = 0.5 V				25	µA
I_EN	EN pin current		V_IN = 6.5 V, V_EN = 0 V and 6.5 V		–0.1		0.1	µA
I_BIAS	BIAS pin current		V_IN = 1.1 V, V_BIAS = 6.5 V, V_OUT(nom) = 0.8 V, I_OUT = 4 A			2.3	3.5	mA
V_IL(EN)	EN pin high-level input voltage (enable device)				0		0.5	V
V_IH(EN)	EN pin low-level input voltage (disable device)				1.1		6.5	V
V_IT(PG)	PG pin threshold		For falling V_OUT		82% × V_OUT	88.3% × V_OUT	93% × V_OUT	V
V_HYS(PG)	PG pin hysteresis		For rising V_OUT			1% × V_OUT		V
V_OL(PG)	PG pin low-level output voltage		V_OUT < V_IT(PG), I_PG = –1 mA (current sunk into pin)				0.4	V
I_lkg(PG)	PG pin leakage current		V_OUT > V_IT(PG), V_PG = 6.5 V				1	µA
I_NR/SS	NR/SS pin charging current		V_NR/SS = GND, V_IN = 6.5 V		4.0	6.2	9.0	µA
I_FB	FB pin leakage current		V_IN = 6.5 V		–100		100	nA
PSRR	Power-supply ripple rejection		V_IN– V_O_UT = 0.5 V, I_OUT = 4 A, C_NR/SS = 100 nF, C_FF = 10 nF, C_OUT = 47 μF \|\| 10 μF \|\| 10 μF	f = 10 kHz, V_OUT= 0.8 V, V_BIAS = 5.0 V		42		dB
				f = 500 kHz, V_OUT = 0.8 V, V_BIAS = 5.0 V		39
				f = 10 kHz, V_OUT = 3.3 V		40
				f = 500 kHz, V_OUT= 3.3 V		25
V_n	Output noise voltage		BW = 10 Hz to 100 kHz, V_IN = 1.2 V, V_OUT = 0.8 V, V_BIAS= 5.0 V, I_OUT = 4 A, C_NR/SS = 100 nF, C_FF = 10 nF, C_OUT = 47 μF \|\| 10 μF \|\| 10 μF			4.4		μV_RMS
V_n	Output noise voltage		BW = 10 Hz to 100 kHz, V_OUT = 5.0 V, I_OUT = 4 A, C_NR/SS = 100 nF, C_FF = 10 nF, C_OUT = 47 μF \|\| 10 μF \|\| 10 μF			8.4		μV_RMS
T_sd	Thermal shutdown temperature		Shutdown, temperature increasing			160		°C
T_sd	Thermal shutdown temperature		Reset, temperature decreasing			140		°C
T_J	Operating junction temperature				–40		125	°C

(2) V_OUT(nom) is the calculated V_OUT target value from the ANY-OUT in a fixed configuration. In an adjustable configuration, V_OUT(nom) is the expected V_OUT value set by the external feedback resistors.

(3) This 50-Ω load is disconnected when the test conditions specify an I_OUT value.

(4) When the device is connected to external feedback resistors at the FB pin, external resistor tolerances are not included.

(5) The device is not tested under conditions where V_IN > V_OUT + 1.25 V and I_OUT = 4 A, because the power dissipation is higher than the maximum rating of the package.

6.6 Typical Characteristics

at T_A = 25°C, V_IN = 1.4 V or V_IN = V_OUT(NOM) + 0.5 V (whichever is greater), V_BIAS = open, V_OUT(NOM) = 0.8 V, V_EN = 1.1 V, C_OUT = 47 μF, C_NR/SS = 0 nF, C_FF = 0 nF, and PG pin pulled up to V_IN with 100 kΩ (unless otherwise noted)

V_IN = 1.2 V, V_BIAS = 5 V,
C_OUT = 47 μF || 10 μF || 10 μF, C_NR/SS = 10 nF, C_FF = 10 nF

Figure 1. PSRR vs Frequency and I_OUT

V_IN = 1.4 V, I_OUT = 1 A,
C_OUT = 47 μF || 10 μF || 10 μF, C_NR/SS = 10 nF, C_FF = 10 nF

Figure 3. PSRR vs Frequency and V_BIAS

V_IN = V_OUT + 0.4 V, V_BIAS = 5.0 V, I_OUT = 4 A,
C_OUT = 47 μF || 10 μF || 10 μF, C_NR/SS = 10 nF, C_FF = 10 nF

Figure 5. PSRR vs Frequency and V_OUT with Bias

V_IN = 5.6 V, C_OUT = 47 μF || 10 μF || 10 μF,
C_NR/SS = 10 nF, C_FF = 10 nF

Figure 7. PSRR vs Frequency and C_OUT

I_OUT = 4 A, C_OUT = 47 μF || 10 μF || 10 μF, C_NR/SS = 10 nF,
C_FF = 10 nF

Figure 9. PSRR vs Frequency and V_IN for V_OUT = 5.0 V

V_IN= V_OUT + 0.4 V and V_BIAS = 5 V for V_OUT ≤ 2.2 V,
C_OUT = 47 μF || 10 μF || 10 μF, C_NR/SS = 10 nF, C_FF = 10 nF

Figure 11. Output Voltage Noise vs Output Voltage

I_OUT = 1 A, C_OUT = 47 μF || 10 μF || 10 μF, C_NR/SS = 10 nF,
C_FF = 10 nF

Figure 13. Output Noise vs Frequency and V_IN

V_IN= V_OUT + 0.4 V, V_BIAS = 5 V, I_OUT = 4 A,
C_OUT = 47 μF || 10 μF || 10 μF, C_NR/SS = 10 nF

Figure 15. Output Noise vs Frequency and C_FF

V_IN = 1.2 V, V_OUT = 0.9 V, V_BIAS = 5.0 V, I_OUT= 4 A,
C_OUT = 47 μF || 10 μF || 10 μF, C_FF = 10 nF

Figure 17. Start-Up Waveform vs Time and C_NR/SS

I_{OUT, DC}= 100 mA, C_OUT = 47 μF || 10 μF || 10 μF,
C_NR/SS = C_FF = 10 nF, slew rate = 1 A/μs

Figure 19. Load Transient Waveform vs Time and
V_OUT without Bias

V_IN = 1.2 V, V_BIAS = 5.0 V, I_OUT = 100 mA to 4 A,
C_NR/SS = C_FF = 10 nF, slew rate = 1 A/μs

Figure 21. Load Transient Waveform vs Time and C_OUT
(V_OUT = 0.9 V)

I_OUT = 4 A, V_BIAS = 0 V

Figure 23. Dropout Voltage vs Input Voltage without Bias

V_IN = 1.4 V, V_BIAS = 0 V

Figure 25. Dropout Voltage vs Output Current without Bias

V_IN = 5.5 V

Figure 27. Dropout Voltage vs Output Current (High V_IN)

Figure 29. Load Regulation (0.8-V Output)

Figure 31. Load Regulation (5-V Output)

V_IN = 1.1 V, I_OUT = 5 mA

Figure 33. Line Regulation vs Bias Voltage

I_OUT = 5 mA

Figure 35. Ground Pin Current vs Input Voltage

Figure 37. Shutdown Current vs Input Voltage

Figure 39. NR/SS Charging Current vs Input Voltage

V_IN = 1.1 V

Figure 41. V_BIAS UVLO vs Temperature

Figure 43. PG Voltage vs PG Current Sink

Figure 45. PG Threshold vs Temperature

I_OUT = 4 A, V_BIAS = 5 V,
C_OUT = 47 μF || 10 μF || 10 μF, C_NR/SS = 10 nF, C_FF = 10 nF

Figure 2. PSRR vs Frequency and V_IN with Bias

I_OUT = 1 A,
C_OUT = 47 μF || 10 μF || 10 μF, C_NR/SS = 10 nF, C_FF = 10 nF

Figure 4. PSRR vs Frequency and V_IN

I_OUT = 4 A, C_OUT = 47 μF || 10 μF || 10 μF, C_NR/SS = 10 nF,
C_FF = 10 nF

Figure 6. PSRR vs Frequency and V_IN for V_OUT = 3.3 V

V_IN = V_OUT + 0.4 V, V_OUT = 1 V, I_OUT = 4 A,
C_OUT = 47 μF || 10 μF || 10 μF, C_NR/SS = 10 nF, C_FF = 10 nF

Figure 8. PSRR vs Frequency and I_OUT for V_OUT = 5.0 V

V_IN = V_OUT + 0.4 V, V_OUT = 1 V, I_OUT = 4 A,
C_OUT = 47 μF || 10 μF || 10 μF, C_NR/SS = 10 nF, C_FF = 10 nF

Figure 10. V_BIAS PSRR vs Frequency

V_IN= V_OUT + 0.4 V and V_BIAS = 5 V for V_OUT ≤ 2.2 V, I_OUT = 4 A, C_OUT = 47 μF || 10 μF || 10 μF, C_NR/SS = 10 nF, C_FF = 10 nF

Figure 12. Output Noise vs Frequency and V_OUT

V_IN= V_OUT + 0.4 V, V_BIAS = 5 V, I_OUT = 4 A,
C_OUT = 47 μF || 10 μF || 10 μF, C_FF = 10 nF

Figure 14. Output Noise vs Frequency and C_NR/SS

V_IN = 5.6 V, I_OUT = 4 A, C_OUT = 47 μF || 10 μF || 10 μF,
C_FF = 10 nF

Figure 16. Output Noise at 5.0-V Output vs C_NR/SS and C_FF

TPS7A85 Load_trans_vs_Vout_with_Bias.gif

V_IN = V_OUT + 0.3 V, V_BIAS = 5 V, I_{OUT, DC}= 100 mA, slew rate = 1 A/μs, C_NR/SS = C_FF = 10 nF, C_OUT = 47 μF || 10 μF || 10 μF

Figure 18. Load Transient Waveform vs Time and
V_OUT with Bias

V_OUT = 5 V, I_{OUT, DC}= 100 mA, I_OUT = 100 mA to 4 A,
C_OUT = 47 μF || 10 μF || 10 μF, C_NR/SS = C_FF = 10 nF

Figure 20. Load Transient Waveform vs Time and
Slew Rate

V_IN = 1.2 V, V_BIAS = 5.0 V, C_OUT = 47 μF || 10 μF || 10 μF,
C_NR/SS = C_FF = 10 nF, slew rate = 1 A/μs

Figure 22. Load Transient Waveform vs Time and DC Load
(V_OUT = 0.9 V)

I_OUT = 4 A, V_BIAS = 6.5 V

Figure 24. Dropout Voltage vs Input Voltage with Bias

V_IN = 1.1 V, V_BIAS = 3 V

Figure 26. Dropout Voltage vs Output Current with Bias

I_OUT = 100 mA to 4 A

Figure 28. Load Regulation vs Output Voltage

Figure 30. Load Regulation (3.3-V Output)

I_OUT = 5 mA

Figure 32. Line Regulation without Bias

I_OUT = 5 mA

Figure 34. Line Regulation (5-V Output)

V_IN = 1.1 V, I_OUT = 5 mA

Figure 36. Bias Pin Current vs Bias Voltage

V_IN = 1.1 V

Figure 38. Shutdown Current vs Bias Voltage

Figure 40. V_IN UVLO vs Temperature

Figure 42. Enable Threshold vs Temperature

V_IN = 6.5 V

Figure 44. PG Voltage vs PG Current Sink