High speed analog to digital converters are notoriously sensitive to power supply noise. The most common solution to minimize that noise is to use linear power supplies, or a switch mode power supply (SMPS) from the main bus rail followed by a low dropout regulator. Compared to a linear supply, there are two big advantages of being able to use a SMPS alone: the reduction in power loss and the size of the power supply. To use a SMPS alone requires careful consideration of the switching supply selected, as well as the design and layout of the SMPS to achieve the desired results of the same performance with lower power dissipation and smaller board space.

This application note uses the ADC12QJ1600-Q1 as an example of a high performance ADC where the supplies have been changed from a SMPS+LDO approach to a SMPS-only approach. This methodology can be used for many other noise sensitive applications as well. The TPS62913 low-ripple and low-noise buck converter used in this application note is specifically designed to help engineers design power supplies that meet the noise and ripple requirements for noise sensitive applications.

The ADC12QJ1600-Q1 is a family of quad, dual and single channel, 12bit, 1.6 GSPS analog-to-digital converter (ADC). Low power consumption and high sample rate make the ADC12QJ1600-Q1 an ideal suite for light detection and ranging (LiDAR) systems. The ADC12QJ1600-Q1 uses a high-speed JESD204C output interface with up to 8 serialized lanes supporting up to 17.16 Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1 and is compatible with JESD204B receivers. Innovative synchronization features, including SYSREF windowing, internal PLL with internal voltage-controlled oscillator (VCO), multi clock outputs for logic and Serdes of FPGA or ASIC, simplify system design for multi-device applications.

The original product evaluation module (EVM) implements low-noise LDOs in addition to the DC/DC buck regulators to minimize any impairments from the supply network. While the DC accuracy of the supply rail is specified for the ADC12QJ1600-Q1, there is no specification on supply voltage noise and supply voltage ripple. Any supply ripple or noise appears attenuated on the output spectrum of the ADC. This attenuation can be expressed as Power Supply Rejection Ration (PSRR) and PSRR_MOD (or PSMR) as shown in Figure 1-1.

PSRR is the attenuation of the ADC input supply ripple to the ADC output spectrum at the switching frequency fundamental of the DC-DC converter (f_DCDC). PSRR_MOD (or PSMR) is the attenuation from the ADC input to the modulated spur in the output spectrum (f_in - f_DCDC, f_in + f_DCDC).

PSRR is usually less of a concern since it is typically >40 dB and outside of the frequency of interest, however some analog rails can have PSRR of <40 dB, as shown in Figure 1-2. Most sensitive supplies of the ADC12QJ1600-Q1 are the analog supply rails of VA11 and VA19. More important is PSMR, since the attenuation from the supply rail to the modulated spur can be low for sensitive analog rails such as VA11 and VA19 on the ADC12QJ1600-Q1.