TLV320ADC5120/PCM5120-Q1 and TLV320AD6120/PCM6120-Q1 devices from TI’s Audio ADC portfolio features an algorithm called Dynamic Range Enhancer (DRE) that can be used to improve the far-field recording performance by improving the dynamic range of the ADC channel at low signal levels. The DRE is a digitally-assisted algorithm that dynamically adjusts the front-end programmable gain amplifier (PGA) to improve the signal-to-noise ratio of low-level signals while preventing high-level signals from saturating the PGA and ADC. Far-field recording performance can also be improved by using a high PGA gain, but it can degrade near-field recording performance since a dynamic change to high-input levels combined with a high fixed-gain PGA can saturate the PGA and ADC. The DRE provides the ability to improve the far-field recording performance without degrading the near-field recording performance. Figure 1-1 shows the improvements in channel performance with DRE. With DRE, the ADC channel performance is not limited by the ADC noise floor and improves the recording performance even for signals below the noise floor of the ADC. Every 6 dB improvement in dynamic range increases the far-field recording distance by a factor of two.

Figure 1-1 DRE Performance

Dynamic Range Compression (DRC) is an algorithm that dynamically adjusts the PGA gain of the ADC channel to expand the signal level over a region of the audio range. A typical example application for DRC occurs while recording speech signals when the speaker is changing his or her distance from the microphone while speaking. Sound pressure levels at the microphone vary inversely with distance to the sound source. Therefore, microphone output levels are weak for the farther sound sources. Without DRC and just a fixed-gain PGA, output levels vary from soft to loud as the person moves closer to the microphone. With DRC enabled, the input level variation below a certain threshold can be maintained at a constant level. Hence, the speech signals which are below a certain threshold are gained up to maintain a constant output so that the weaker speech signals can be recorded properly. Thus, DRC automatically responds to changes in the input signal below a certain threshold to maintain a fixed level to meet target application requirements. Figure 2 shows output vs input plot when the DRC disabled as well as enabled.

Figure 1-2 DRC Performance

DRE and DRC is supported on all ADC channels of TLV320ADC5120/PCM5120-Q1 and TLV320ADC6120/PCM6120-Q1 devices. This application note describes the operation of the DRE and DRC, the tunable parameters, and the device configurations required to use DRE/DRC.

Figure 2-1 shows the signal processing chain for TLV320ADC5120/PCM5120-Q1 and TLV320ADC6120/PCM6120-Q1 devices. The dynamic range performance of the front-end PGA in TLV320ADC5120/PCM5120-Q1 and TLV320ADC6120/PCM6120-Q1 devices are 120 dB and 122 dB respectively. The subsequent delta-sigma ADC has 108 dB dynamic range for the TLV320ADC5120 /PCM3120-Q1 and 113 dB dynamic range for the TLV320ADC6120/PCM6120-Q1 .Without the DRE, the ultra-low noise performance of the PGA is limited by the ADC performance and the overall channel dynamic range is determined by the dynamic range of the ADC. With the DRE, the overall channel dynamic range can be improved beyond the dynamic range of the ADC and is limited more by the dynamic range of the PGA.

Figure 2-1 Signal Processing Block Diagram

The DRE algorithm monitors the input signal and increases the gain of the analog PGA for signal levels below a threshold. At the same time, the DRE algorithm creates a corresponding reciprocal attenuation in the digital circuits so the net effect of the analog PGA gain and digital attenuation cancel each other out. Thus the DRE improves the dynamic range without increasing the overall channel gain. The DRE does not gain signals above the threshold. Boosting the low-level signals in analog keeps the input to the ADC significantly above its noise floor and thus prevents the ADC performance from being the limiting factor. Subsequent processing is done using a high-performance, 32-bit, digital signal processor with very low quantization noise, and, therefore, the PGA performance becomes the limiting factor in the overall channel performance. TLV320ADC5120 /PCM5120-Q1 and TLV320ADC6120/PCM6120-Q1 devices support up to four analog input channels. All analog input channels support DRE. The devices support differential or single-ended signals from an analog microphone source or auxiliary line input. The analog microphone inputs support electret condenser and microelectrical-mechanical (MEMS) microphones. Even though the devices also support digital pulse density modulated (PDM) digital microphones, the DRE/DRC does not support the digital channels as the analog gain of the digital microphone cannot be controlled. The TLV320ADCx120/PCMx120-Q1 family of devices also support an automatic gain control (AGC) algorithm on the analog channels to maintain a constant nominal output level. AGC, DRE and DRC algorithms cannot be used simultaneously since all these algorithms control the PGA. DRE or AGC selection is done using AGC_DRE_SEL field of DSP_CFG1 register (page = 0x00, address = 0x6C) as shown inTable 2-1.