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  • AM62Ax/AM62Dx Escape Routing for PCB Design

    • SPRUJ81A February   2023  – January 2025 AM62A1-Q1 , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62D-Q1

       

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  • AM62Ax/AM62Dx Escape Routing for PCB Design
  1.   1
  2.   Trademarks
  3. 1 Introduction
  4. 2 Width/Spacing Proposal for Escapes
  5. 3 Stackup
  6. 4 Via Sharing
  7. 5 Floorplan Component Placement
  8. 6 Critical Interfaces Impact Placement
  9. 7 Routing Priority
  10. 8 SerDes Interfaces
  11. 9 DDR Interfaces
  12. 10Power Decoupling
  13. 11Route Lowest Priority Interfaces Last
  14. 12Summary
  15. 13References
  16. 14Revision History
  17. IMPORTANT NOTICE
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User's Guide

AM62Ax/AM62Dx Escape Routing for PCB Design

Trademarks

All trademarks are the property of their respective owners.

1 Introduction

The AM62Ax/AM62Dx are based on the Cortex-A53 microprocessor, M4F microcontroller with dedicated peripherals, 3D graphics acceleration, dual display interfaces, and extensive peripheral and networking options for a variety of embedded applications. The AM62Ax is available in a 18-mm × 18-mm FBGA package with a 0.8-mm ball pitch. The package BGA design is built leveraging TI Flip Chip BGA Technology (FC-BGA) technology. The AM62Dx is available in a 18-mm × 18-mm FCCSP package with a 0.8-mm ball pitch. Device-specific data sheets should be referenced to document specific features and package availability.

This document is intended to provide a reference for escape routing on the AM62Ax and AM62Dx device. Care must be taken to route signals with special requirements such as DDR, high speed interfaces. for more information, see the High-Speed Interface Layout Guidelines and DDR Routing Guidelines. Details on Power Delivery Network are provided in Sitara Processor Power Distribution Networks: Implementation and Analysis and any routing and layout requirements specified in those documents supersede the generic requirements provided here.

 

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