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Five-Ethernet-Port Enablement on AM64x and AM243x
SPRADH8
September 2024
AM6442
CONTENTS
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Five-Ethernet-Port Enablement on AM64x and AM243x
1
Abstract
Trademarks
1
Introduction
1.1
AM64x and AM243x EVMs
1.2
SoC Architecture
1.2.1
AM64x
1.2.2
AM243x
1.3
Peripherals
1.3.1
CPSW3G
1.3.2
PRU-ICSSG
1.4
Ethernet Software Architecture
1.5
Prerequisite
1.5.1
HW Prerequisite
1.5.2
SW Prerequisite
1.5.2.1
Resource Allocation - AM64x
1.5.2.2
SBL update
2
Multicore 5-Ethernet Ports Realization
3
Supported Configurations on PRU-ICSSG
4
Implementation
4.1
System Example
4.1.1
Software Architecture
4.1.2
5-Ethernet Port Example
5
Debug Steps
6
Reference Logs
7
Testing for the ICSSG0 and ICSSG1 Functionality
8
ICSSG and CPSW
9
Summary
10
References
IMPORTANT NOTICE
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Application Note
Five-Ethernet-Port Enablement on AM64x and AM243x