C2000™ Hardware Built-In Self-Test

1 C2000™ Hardware Built-In Self-Test

This application note discusses the Hardware Built-In Self-Test (HWBIST) feature in C2000™ real-time controllers. The HWBIST provides a method of reaching a high level of diagnostic coverage on the C28x CPU, which is often needed to satisfy safety standards.

Trademarks

C2000™ and Code Composer Studio™ are trademarks of Texas Instruments.

All trademarks are the property of their respective owners.

1 Introduction

HWBIST refers to circuitry and scan patterns generated by an ATPG tool used to screen out logic failures within the targeted circuitry. This methodology is used extensively in semiconductor device testing. All C2000 devices make use of some level of hardware-assisted test during device manufacturing. Some of the newer C2000 devices support customer use of this test technology as part of their system test, to test the integrity of the CPUs (US 8,799,713 B2). This document describes how and why to make use of HWBIST at a system level.

Table 1-1 lists the terms and abbreviations used in this application report.

Table 1-1 Terms and Abbreviations

Abbreviation	Term
ATPG	Automatic test pattern generation
BIST	Built-In Self-Test
Capture	The embedded circuitry capturing the results of the changing logic as the seeds are clocked through the logic under test
C28x	The name of the core 32-bit CPU in TMS320C28x devices
CS	Code Composer Studio™
CLA	Control Law Accelerator
Context restore	The process of restoring the central processing unit (CPU) registers and status flags after completing a hardware BIST micro-run. This is performed by the software.
Context save	The process of saving the CPU registers and status flags before starting a hardware BIST micro-run. This is performed by the software.
Core bounding	The CPU core is disconnected from peripherals and interrupt signals during a micro-run test. After the test, the core is reconnected to these signals.
Coverage	The percentage of the CPU logic that is covered by the hardware BIST.
CPU	Central processing unit
CRC	Cyclical redundancy check
DC	Diagnostic coverage
Flash	Nonvolatile on-chip memory
FPU	Floating point unit
HWBIST	Hardware Built-In Self-Test
ISR	Interrupt service routine
JTAG	Joint test action group. JTAG is a scan-based communications protocol (like I2C) which allows for scanning to either test circuitry or emulation circuitry.
Micro-run	Execution of a portion of a full HWBIST test execution. The HWBIST is designed to support executing the full coverage test in pieces to better manage interrupt latency and power. These micro-runs must be executed in smaller time-slices for more efficient task scheduling. During a micro-run, the CPU is isolated from all peripherals and memory. In addition, interrupts are logged by the HWBIST controller.
MISR	Multiple-input signature-register
NMI	Nonmaskable interrupt
PEST	Periodic self-test
PLL	Phase-locked loop
POR	Power-on reset
POST	Power-on self-test
RAM	Random access memory
ROM	Read-only memory
Seed	Initial states which are loaded into the circuitry using scan paths, so that the circuitry starts out in a known state before testing begins
Semaphore	A mechanism to acquire write access to certain self-test registers by CPU1 or CPU2 used on multi-core devices
SDL	Software Diagnostic Library
STL	Self-Test Library
TMU	Trigonometric math unit
TRM	Technical reference manual
VCU	Viterbi and complex math unit

On C2000 devices that have HWBIST, the HWBIST targets the C28x CPU and the FPU, VCU, CRC, and TMU accelerators. Also included is the emulation analysis circuitry, which manages communications between these processing elements and the emulator, as well as manages features like breakpoints, watch points, and single stepping.

The HWBIST does not target the rest of the logic on the device. The other logic on the device may be tested with other self-test or diagnostic mechanisms as described in the device-specific safety manual.

For the availability of HWBIST, see the device-specific data sheet. You can also check the documents below for HWBIST and other functional safety features and collateral:

While this document focuses on HWBIST, for functional safety compliant C2000 devices without HWBIST (like those in the F28004x device family), a C28x Self-Test Library (C28x STL) is provided to test the integrity of the CPU logic using a software-based method. Similarly, HWBIST does not cover the Control Law Accelerator (CLA), so for devices with CLA, a separate CLA Self-Test Library (CLA STL) is available. These libraries are provided upon request—reach out to your local TI Sales Person to request access.

1.1 HWBIST Overview

Figure 1-1 shows a block diagram of HWBIST, as used in the C2000 device. The orange and pink portions show the logic targeted for testing. In system use, this logic is the processing engine for the system code. Data flows through the latches as the executing system code instructs.

Figure 1-1 HWBIST Block Diagram

However, these same latches include scan access so that during tests of this logic, a high-speed test flow can validate the operation of the gates in the circuitry. In the case discussed here there are many parallel scan paths through the logic so that significant portions of the logic can be tested in parallel. While in this test mode, the logic does not operates like the processor would when running code.

The Pattern Generator provides seeds to these parallel scan paths to provide activity necessary to logically validate the operation of the targeted gates. These seeds are computer generated and the coverage is validated with standard ATPG tools. The seeds are optimized to meet a particular fault grade target in a minimum number of cycles. The vendors of these optimizers take great pride in this optimization.

Note: This optimization means the switching rates of the transistors is significantly higher than those occurring when this logic is executing system code. Additionally, this provides very high fault coverage.

The capture and MISR portion picks up the results of the scanning operation across all the parallel chains. The interaction of the stepping of the scan patterns through the paths interacts with other logic gates in the circuitry tied to the latches. The optimization software injects faults into the gates, and if the MISR does not recognize a failure, then additional seeds are necessary to validate the faulted gate. The optimizer is given a coverage target and will continue to generate seeds until this metric is met. Reaching coverage of 60% is relatively simple; reaching 95% takes significantly more seeds, and reaching 99% requires significantly more seeds than 95% does.

Note: As the bits are driven through the parallel scan paths, the contexts of all the targeted latches are changed multiple times. Stated differently, any context in these latches before testing is completely lost during the test. The context is restored through a combination of hardware logic and software.

The clocking of the scan operations is driven by SYSCLK. The BIST controller manages how the data is shifted and clocked during the scan flow. The BIST controller also manages the loading of seeds and comparison values for the MISR. In device manufacturing test flow, the BIST controller and clock source are established using a device test port like JTAG.

This is an oversimplified description of this testing methodology. A number of detailed and scholarly articles on scan-based testing are available on the web.