SNVAA21 August 2021 LM61480-Q1 , LM61495-Q1 , LM62460 , LM62460-Q1
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Every buck regulator will have a specified maximum output current rating capability that the device can handle before an over-current condition is triggered. In this over-current condition the device will shut-down, stop switching, and check if the fault is removed before switching is resumed. Normally if a design calls for a higher output current requirement above the device’s maximum rated output current limit, a new device must be selected. However this would require a new schematic and PCB layout design if the device is not pin-to-pin compatible with the original layout.
With a simple external differential op-amp circuit two single-output buck regulators can be configured in a two-phase design to allow twice the load current capability of a single buck regulator. This provides customers the following benefits:
Two commonly used methods for sensing current in the power stage of a buck converter are the use of current sense resistors and inductor DCR current sensing. The benefit of using the current sense resistor method is superior accuracy over the entire operating conditions (for example, variations in inductor DCR and inductance values between the two channels) and better matched current sharing between the two phases, while sacrificing power loss. On the other hand, DCR current sensing sacrifices accuracy while being more efficient, since there is typically negligible power loss associated with this method of sensing. The application requirements will dictate which current sensing method will be implemented.
When using the inductor DCR current sensing method, a carefully selected RC network is used to mimic or recreate the voltage that would be seen across the DCR of the inductor. It is as if the DCR of the inductor is the current sense resistor. In order to accurately represent the current flowing through the DCR, the RC time constant (τ), needs to be the same as that of the inductor and DCR
One of the ways to find the values for the RC components is by first calculating an approximate resistor value for R (Rtemporary), from which we will find the capacitor value. Once an actual capacitor is selected (i.e from a component vendor), we can then re-calculate a more accurate resistor value. The reason for performing this slightly iterative process is due to the fact that it is usually more difficult to find a capacitor with the desired value, temperature coefficient, voltage rating, and availability, compared to the resistor.
The power loss through the current sense resistor involves the maximum continuous load current, which for a buck converter is the average inductor current at this condition.
For example, in the case of PMP22993, the maximum peak load current (per phase) is 6A, giving us a peak inductor current of 7AIL_pk. Figure 2-1 is a GUI from the Power Stage Designer Tool to help illustrate and simulate the expected inductor current given a typical design value (VIN = 16V, VOUT = 3.3V, IOUT = 6A, Fsw = 2.1MHz).
If we were to use 100mV as the full-scale current sense voltage we get,
Now let us see how much power will be dissipated in this resistor when operating at the maximum continuous load current:
Let us check how much this amount of power loss will decrease our total system efficiency:
For this application, a loss of 2% of efficiency at maximum continuous load is deemed acceptable. Designing for a reduced system efficiency of 3% or lower is generally acceptable but will depend on the application requirements. As a rule-of-thumb, it is always good to select a current sense resistor that has a power dissipation rating that is twice that of the calculated power loss. This is so that the resistor temperature does not get too high.
To assist in calculating, as well as visualizing, many of the signals associated with switch-mode power supplies, such as the peak inductor current, please download Power Stage Designer (link).
Current sharing between two buck regulators can be achieved using a simple current sharing op-amp circuit using a OPA991. This current sharing amplifier design is configured as a differential amplifier which compares the primary and secondary phase inductor currents. The op amp circuit servos the secondary converter's load current, by controlling the output voltage, to keep the difference between the primary and secondary output currents zero. For example, if the primary phase were to source more current than the secondary phase, the output of the differential amplifier will decrease causing the secondary phase voltage to slightly increase. This results in the secondary phase sourcing more current until it achieves balanced current sharing.
R2 and RF should be calculated such that, when the primary and secondary output voltage is matched, the output of the difference amplifier is equal to the reference voltage (Vref) of the buck regulator (Refer to schematic in Figure 3-1 for more details). When both phases are evenly matched no current will be sourced or sinked from the feedback node. Note that the op-amp current sense design requires a compensation capacitor that is placed in parallel to RF. This capacitor value may need to be adjusted per application parameters.