SNLA426 june 2023 DS320PR1601 , DS320PR410 , DS320PR810 , SN75LVPE5412 , SN75LVPE5421
This application note helps system designers implement best practices and understand PCB layout options when designing high-speed PCI Express (PCIe) platforms. This document is intended for audiences familiar with PCB manufacturing, layout, and design. A successful Gen5 x16 lane design requires a PCB layout with a mindset for optimization of crosstalk, return loss, and insertion loss.
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Peripheral Component Interconnect Express (PCIe) was introduced over two decades ago to enable the growing demand for high bandwidth/speed data transfers. Each new generation for PCIe has effectively doubled the rate of transmission. The current generation, PCIe Gen5, transfers data at a rate of 32 GT/s. High speed interfaces such as PCIe introduced many challenges in regards to layout, including but not limited to traces, vias, reference planes, dielectrics, and so on. All of the factors mentioned previously have significant impacts at high data rates; thus, adhere to the following layout practices to overcome PCIe Gen5 layout challenges.