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  • ADS41xx 14-, 12-Bit, 65-, 125-MSPS, Ultra-Low-Power ADC

    • SBAS520C February   2011  – June 2017 ADS4122 , ADS4125 , ADS4142 , ADS4145

      PRODUCTION DATA.  

  • CONTENTS
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  • ADS41xx 14-, 12-Bit, 65-, 125-MSPS, Ultra-Low-Power ADC
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Family Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: ADS412x
    6. 7.6  Electrical Characteristics: ADS414x
    7. 7.7  Electrical Characteristics: General
    8. 7.8  Digital Characteristics
    9. 7.9  Timing Requirements: LVDS and CMOS Modes
    10. 7.10 Serial Interface Timing Characteristics
    11. 7.11 Reset Timing Requirements
    12. 7.12 Timing Characteristics at Lower Sampling Frequencies
    13. 7.13 Typical Characteristics: ADS4122
    14. 7.14 Typical Characteristics: ADS4125
    15. 7.15 Typical Characteristics: ADS4142
    16. 7.16 Typical Characteristics: ADS4145
    17. 7.17 Typical Characteristics: Common
    18. 7.18 Typical Characteristics: Contour
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Digital Functions and Low-Latency Mode
      2. 8.3.2 Gain for SFDR, SNR Trade-Off
      3. 8.3.3 Offset Correction
      4. 8.3.4 Power-Down
        1. 8.3.4.1 Power-Down Global
        2. 8.3.4.2 Standby
        3. 8.3.4.3 Output Buffer Disable
        4. 8.3.4.4 Input Clock Stop
      5. 8.3.5 Output Data Format
    4. 8.4 Device Functional Modes
      1. 8.4.1 Digital Output Information
        1. 8.4.1.1 Output Interface
        2. 8.4.1.2 DDR LVDS Outputs
        3. 8.4.1.3 LVDS Output Data and Clock Buffers
        4. 8.4.1.4 Parallel CMOS Interface
        5. 8.4.1.5 CMOS Interface Power Dissipation
    5. 8.5 Programming
      1. 8.5.1 Device Configuration
      2. 8.5.2 Serial Interface
        1. 8.5.2.1 Register Initialization
      3. 8.5.3 Serial Register Readout
    6. 8.6 Register Maps
      1. 8.6.1 Serial Register Map
      2. 8.6.2 Description of Serial Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Analog Input
        1. 9.1.1.1 Drive Circuit Requirements
        2. 9.1.1.2 Driving Circuit
        3. 9.1.1.3 Input Common-Mode
      2. 9.1.2 Clock Input
      3. 9.1.3 Input Overvoltage Indication (OVR Pin)
      4. 9.1.4 Using the ADS41xx at Low Sampling Rates
        1. 9.1.4.1 ADS412x (12-Bit Device)
        2. 9.1.4.2 ADS414x (14-Bit Device)
        3. 9.1.4.3 Power Consumption at Low Sampling Rates
        4. 9.1.4.4 Output Timing at Low Sampling Rates
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Analog Input
        2. 9.2.2.2 Clock Driver
        3. 9.2.2.3 Digital Interface
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Sharing DRVDD and AVDD Supplies
    2. 10.2 Using DC-DC Power Supplies
    3. 10.3 Power Supply Bypassing
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Grounding
      2. 11.1.2 Supply Decoupling
      3. 11.1.3 Exposed Pad
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Community Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE
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DATA SHEET

ADS41xx 14-, 12-Bit, 65-, 125-MSPS, Ultra-Low-Power ADC

1 Features

  • Ultra-Low Power With 1.8-V Single Supply:
    • 103-mW Total Power at 65 MSPS
    • 153-mW Total Power at 125 MSPS
  • High Dynamic Performance:
    • SNR: 72.2 dBFS at 170 MHz
    • SFDR: 81 dBc at 170 MHz
  • Dynamic Power Scaling With Sample Rate
  • Idle Channel SNR 74.8 dBFS (ADS414x)
  • Output Interface:
    • Double Data Rate (DDR) LVDS With Programmable Swing and Strength:
      • Standard Swing: 350 mV
      • Low Swing: 200 mV
      • Default Strength: 100-Ω Termination
      • 2x Strength: 50-Ω Termination
    • 1.8-V Parallel CMOS Interface Also Supported
  • Programmable Gain up to 6 dB for SNR, SFDR Trade-Off
  • DC Offset Correction
  • Supports Low Input Clock Amplitude Down to 200 mVPP

2 Applications

  • Wireless Communications Infrastructure
  • Software-Defined Radios
  • Power Amplifier Linearization
  • Imaging Systems

3 Description

The ADS412x and ADS414x devices are lower-sampling speed variants in the ADS41xx family of analog-to-digital converters (ADCs). These devices use innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8-V supply. The devices are well-suited for multi-carrier, wide bandwidth communications applications.

The ADS412x and ADS414x devices have fine gain options that can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. They include a dc offset correction loop that can be used to cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled down power with no loss in performance.

The ADS412x and ADS414x devices are available in a compact VQFN-48 package and are specified over the industrial temperature range (–40°C to +85°C).

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
ADS4122 VQFN (48) 7.00 mm × 7.00 mm
ADS4125
ADS4142
ADS4145
  1. For all available packages, see the orderable addendum at the end of the data sheet.

ADS41xx Block Diagram

ADS4122 ADS4125 ADS4142 ADS4145 ADS4122_Front_Page_Figure.gif

4 Revision History

Changes from B Revision (January 2016) to C Revision

  • Added a new feature Idle Channel SNR 74.8 dBFS (ADS414x) to the Features sectionGo
  • Added a new application Imaging Systems in Applications sectionGo
  • Changed ADS412x/4x to ADS412x and ADS414x in Description sectionGo
  • Changed ADS41xx Block Diagram in the first page.Go
  • Changed input clock sample rate minimum for the ADS4122/ADS4142, low-speed mode enabled by default from: 20 MSPS to: 3 MSPS Go
  • Changed input clock sample rate minimum for the ADS4122/ADS4142, low-speed mode enabled from: 20 MSPS to: 3 MSPS Go
  • Deleted High Performance Modes section from Recommended Operating Conditions table, moved to Programming sectionGo
  • Added order to HD2 and HD3 parameter names in Electrical Characteristics tablesGo
  • Added test conditions header to Electrical Characteristics: General table Go
  • Added Using the ADS41xx at Low Sampling Rates subsection in Application and Implementation sectionGo
  • Added Figure 114 to Figure 124 in ADS412x (12-Bit Device) sectionGo
  • Changed the order of figures in ADS412x (12-Bit Device) section. Go
  • Added the device name ADS412x to the conditions of ADS412x (12-Bit Device) section.Go
  • Changed the unit of fS from MHz to MSPS in the specifications of Figure 115Go
  • Added new subsection ADS412x (12-Bit Device) in Application Information section. Go
  • Changed the unit of fS from MHz to MSPS in the specifications of Figure 116Go
  • Changed the unit of fS from MHz to MSPS in the specifications of Figure 119 Go
  • Changed the unit of fS from MHz to MSPS in the specifications of Figure 120 Go
  • Changed the unit of fS from MHz to MSPS in the specifications of Figure 121 Go
  • Changed the unit of fS from MHz to MSPS in the specifications of Figure 122 Go
  • Added Figure 125 through Figure 128 in typical performance at lower sampling rate for ADS412x (12-bit devices) in CMOS interface mode. Go
  • Added Figure 129 through Figure 130 in typical performance at lower sampling rate for ADS412x (12-bit devices) in CMOS interface mode. Go
  • Added Figure 131 through Figure 132 in typical performance at lower sampling rate for ADS412x (12-bit devices) in CMOS interface mode. Go
  • Added Figure 136 to Figure 146 in ADS414x (14-Bit Device) sectionGo
  • Changed the order of figures in ADS414x (14-Bit Device) section.Go
  • Added the device name ADS414x to the conditions of ADS414x (14-Bit Device) section. Go
  • Changed the unit of fS from MHz to MSPS in the specifications of Figure 137 and Figure 138Go
  • Added new subsection ADS414x (14-Bit Device) in Application Information section.Go
  • Changed the SNR and SINAD values of Figure 138 .Go
  • Changed the unit of fS from MHz to MSPS in the specifications of Figure 141 through Figure 144Go
  • Added Figure 147 through Figure 157 in typical performance at lower sampling rate for ADS414x (14-bit devices) in CMOS interface mode. Go
  • Added Figure 151 through Figure 158 in typical performance at lower sampling rate for ADS414x (14-bit devices) in CMOS interface mode. Go
  • Added Figure 153 through Figure 155 in typical performance at lower sampling rate for ADS414x (14-bit devices) in CMOS interface mode. Go
  • Added Output Timing at Low Sampling Rates subsection in Application and Implementation sectionGo
  • Changed the name of the header from ADS4128 CAPABILITY to ADS4125 CAPABILITY in the last column of Table 10 Go
  • Added Receiving Notification of Documentation Updates section Go

Changes from A Revision (March 2011) to B Revision

  • Added Pin Configuration and Functions section, Handling Rating table, Feature Descriptionsection, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Supportsection, and Mechanical, Packaging, and Orderable Information section Go

5 Device Family Comparison

FAMILY 65 MSPS 125 MSPS 160 MSPS 250 MSPS WITH ANALOG INPUT BUFFERS
200 MSPS 250 MSPS
ADS412x,
12-bit family		 ADS4122 ADS4125 ADS4126 ADS4129 — ADS41B29
ADS414x,
14-bit family		 ADS4142 ADS4145 ADS4146 ADS4149 — ADS41B49
9-Bit — — — — — ADS58B19
11-Bit — — — — ADS58B18 —

 
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