• Menu
  • Product
  • Email
  • PDF
  • Order now

  • LM5175、42V、広VIN 4スイッチ同期整流昇降圧コントローラ

    • JAJSC20A October   2015  – May 2016 LM5175

      PRODUCTION DATA.  

  • CONTENTS
  • SEARCH
  • LM5175、42V、広VIN 4スイッチ同期整流昇降圧コントローラ
  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 概略回路図
  5. 5 改訂履歴
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed Frequency Valley/Peak Current Mode Control with Slope Compensation
      2. 8.3.2  VCC Regulator and Optional BIAS Input
      3. 8.3.3  Enable/UVLO
      4. 8.3.4  Soft-Start
      5. 8.3.5  Overcurrent Protection
      6. 8.3.6  Average Input/Output Current Limiting
      7. 8.3.7  CCM/DCM Operation
      8. 8.3.8  Frequency and Synchronization (RT/SYNC)
      9. 8.3.9  Frequency Dithering
      10. 8.3.10 Output Overvoltage Protection (OVP)
      11. 8.3.11 Power Good (PGOOD)
      12. 8.3.12 Gm Error Amplifier
      13. 8.3.13 Integrated Gate Drivers
      14. 8.3.14 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown, Standby, and Operating Modes
      2. 8.4.2 MODE Pin Configuration
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Frequency
        2. 9.2.2.2  VOUT
        3. 9.2.2.3  Inductor Selection
        4. 9.2.2.4  Output Capacitor
        5. 9.2.2.5  Input Capacitor
        6. 9.2.2.6  Sense Resistor (RSENSE)
        7. 9.2.2.7  Slope Compensation
        8. 9.2.2.8  UVLO
        9. 9.2.2.9  Soft-Start Capacitor
        10. 9.2.2.10 Dither Capacitor
        11. 9.2.2.11 MOSFETs QH1 and QL1
        12. 9.2.2.12 MOSFETs QH2 and QL2
        13. 9.2.2.13 Frequency Compensation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報
  14. 重要なお知らせ
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
  • Card with all content

 

DATA SHEET

LM5175、42V、広VIN 4スイッチ同期整流昇降圧コントローラ

このリソースの元の言語は英語です。 翻訳は概要を便宜的に提供するもので、自動化ツール (機械翻訳) を使用していることがあり、TI では翻訳の正確性および妥当性につきましては一切保証いたしません。 実際の設計などの前には、ti.com で必ず最新の英語版をご参照くださいますようお願いいたします。

1 特長

  • 昇降圧DC/DC変換用のシングル・インダクタ昇降圧コントローラ
  • 広いVIN範囲: 3.5V～42V、最大60V
  • 柔軟なVOUT範囲: 0.8V～55V
  • VOUT短絡保護
  • 高効率の昇降圧遷移
  • 可変スイッチング周波数
  • オプションの周波数同期とディザリング
  • 2AのMOSFETゲート・ドライバを内蔵
  • サイクル毎の電流制限およびオプションのヒカップ機能
  • 入力または出力平均電流制限(オプション)
  • プログラミング可能な入力UVLOおよびソフト・スタート
  • パワー・グッドおよび出力過電圧保護
  • CCMまたはDCM (パルス・スキップ付き)を選択可能
  • HTSSOP-28およびQFN-28パッケージで利用可能

2 アプリケーション

  • 車載向け始動/停止システム
  • バックアップ・バッテリおよびスーパーキャパシタの充電
  • 産業用PC電源
  • USB配電
  • LEDライティング

3 概要

LM5175は、同期整流4スイッチ昇降圧DC/DCコントローラであり、出力電圧を入力電圧と同じ値、より高い値、より低い値のいずれにも制御できます。LM5175は、3.5V～42V (最大60V) という幅広い範囲の入力電圧で動作し、さまざまなアプリケーションをサポートします。

LM5175は、降圧モードと昇圧モードの両方で電流モード制御を採用し、優れたロード・レギュレーション、ライン・レギュレーションを実現します。スイッチング周波数は、外付け抵抗を使ってプログラミングするか、または外部クロック信号に同期させることができます。

また、プログラマブル・ソフト・スタート機能を備えるほか、サイクル毎の電流制限、入力低電圧誤動作防止(UVLO)、出力過電圧保護(OVP)、過熱シャットダウンなどの保護機能も搭載しています。さらに、LM5175は、選択可能な連続導通モード(CCM)または不連続導通モード(DCM)動作に加え、平均入力/出力電流制限、スペクトラム拡散によるピークEMI低減、過負荷状態が持続した場合のヒカップ・モード保護といった機能をオプションでサポートしています。

製品情報

発注型番 パッケージ 本体サイズ
LM5175PWP HTSSOP-28 9.7mm×4.4mm
LM5175RHF QFN-28 4.0mm×5.0mm

4 概略回路図

LM5175 schematic_frontpage.gif

5 改訂履歴

Changes from * Revision (October 2015) to A Revision

  • Added QFN-28パッケージGo
  • Added LM5175RHFの製品情報Go
  • Added RHF packageGo
  • Added QFN pins Go
  • Changed first plus to minus Go
  • Changed all 1.22 V to 1.23 V Go
  • Changed equation Go
  • Changed equation Go
  • Changed equation Go

6 Pin Configuration and Functions

HTSSOP-28
PWP Package
Top View
LM5175 po1_PWP_snvsa37.gif
QFN-28
RHF Package
Top View
LM5175 po2_RHF_snvsa37.gif

Pin Functions

PIN DESCRIPTION
NAME HTSSOP QFN
EN/UVLO 1 26 Enable pin. For EN/UVLO < 0.4 V, the LM5175 is in a low current shutdown mode. For 0.7 V < EN/UVLO < 1.23 V, the controller operates in standby mode in which the VCC regulator is enabled but the PWM controller is not switching. For EN/UVLO > 1.23 V, the PWM function is enabled, provided VCC exceeds the VCC UV threshold.
VIN 2 27 The input supply pin to the IC. Connect VIN to a supply voltage between 3.5 V and 42 V.
VISNS 3 28 VIN sense input. Connect to the input capacitor.
MODE 4 1 Mode = GND, DCM, Hiccup Disabled (Set RMODE resistor to GND = 0 Ω)
Mode = 1.00 V, DCM, Hiccup Enabled (Set RMODE resistor to GND = 49.9 kΩ)
Mode = 1.85 V, CCM, Hiccup Enabled (Set RMODE resistor to GND = 93.1 kΩ)
Mode = VCC, CCM, Hiccup Disabled (Set RMODE resistor to VCC = 0 Ω)
DITH 5 2 A capacitor connected between the DITH pin and AGND is charged and discharged with a 10 uA current source. As the voltage on the DITH pin ramps up and down the oscillator frequency is modulated between –5% and +5% of the nominal frequency set by the RT resistor. Grounding the DITH pin will disable the dithering feature. In the external Sync mode, the DITH pin voltage is ignored.
RT/SYNC 6 3 Switching frequency programming pin. An external resistor is connected to the RT/SYNC pin and AGND to set the switching frequency. This pin can also be used to synchronize the PWM controller to an external clock.
SLOPE 7 4 A capacitor connected between the SLOPE pin and AGND provides the slope compensation ramp for stable current mode operation in both buck and boost mode.
SS 8 5 Soft-start programming pin. A capacitor between the SS pin and AGND pin programs soft-start time.
COMP 9 6 Output of the error amplifier. An external RC network connected between COMP and AGND compensates the regulator feedback loop.
AGND 10 7 Analog ground of the IC.
FB 11 8 Feedback pin for output voltage regulation. Connect a resistor divider network from the output of the converter to the FB pin.
VOSNS 12 9 VOUT sense input. Connect to the output capacitor.
ISNS(–)
ISNS(+)		 13
14		 10
11		 Input or Output Current Sense Amplifier inputs. An optional current sense resistor connected between ISNS(+) and ISNS(–) can be located either on the input side or on the output side of the converter. If the sensed voltage across the ISNS(+) and ISNS(-) pins reaches 50 mV, a slow Constant Current (CC) control loop becomes active and starts discharging the soft-start capacitor to regulated the drop across ISNS(+) and ISNS(-) to 50 mV. Short ISNS(+) and ISNS(-) together to disable this feature.
CSG 15 12 The negative or ground input to the PWM current sense amplifier. Connect directly to the low-side (ground) of the current sense resistor.
CS 16 13 The positive input to the PWM current sense amplifier.
PGOOD 17 14 Power Good open drain output. PGOOD is pulled low when FB is outside a 0.8 V ±10% regulation window.
SW2
SW1		 18
28		 15
25		 The boost and the buck side switching nodes respectively.
HDRV2
HDRV1		 19
27		 16
24		 Output of the high-side gate drivers. Connect directly to the gates of the high-side MOSFETs.
BOOT2
BOOT1		 20
26		 17
23		 An external capacitor is required between the BOOT1, BOOT2 pins and the SW1, SW2 pins respectively to provide bias to the high-side MOSFET gate drivers.
LDRV2
LDRV1		 21
25		 18
22		 Output of the low-side gate drivers. Connect directly to the gates of the low-side MOSFETs.
PGND 22 19 Power ground of the IC. The high current ground connection to the low-side gate drivers.
VCC 23 20 Output of the VCC bias regulator. Connect capacitor to ground.
BIAS 24 21 Optional input to the VCC bias regulator. Powering VCC from an external supply instead of VIN can reduce power loss at high VIN. For VBIAS > 8 V, the VCC regulator draws power from the BIAS pin. The BIAS pin voltage must not exceed 40 V.
PowerPAD™ - - The PowerPAD should be soldered to the analog ground. If possible, use thermal vias to connect to a PCB ground plane for improved power dissipation.

7 Specifications

7.1 Absolute Maximum Ratings(1)

MIN MAX UNIT
VIN, EN/UVLO, VISNS, VOSNS, ISNS(+), ISNS(–) –0.3 60 V
BIAS –0.3 40
FB, SS, DITH, RT/SYNC, SLOPE, COMP –0.3 3.6
SW1, SW2 –1 60
SW1, SW2 (20 ns transient) –3.0 65
VCC, MODE, PGOOD –0.3 8.5
LDRV1, LDRV2 –0.3 8.5
BOOT1, HDRV1 with respect to SW1 –0.3 8.5
BOOT2, HDRV2 with respect to SW2 –0.3 8.5
BOOT1, BOOT2 –0.3 68
CS, CSG –0.3 0.3
Operating junction temperature –40 150 °C
Storage temperature, Tstg -65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
VESD(1) Human body model (HBM) ESD stress voltage(2) ±2000 V
Charged device model (CDM) ESD stress voltage(3) ±750
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges into the device.
(2) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN NOM MAX UNIT
VIN Input voltage range 3.5 42 V
BIAS Bias supply voltage range 8 36
VOUT Output voltage range 0.8 55
EN/UVLO Enable voltage range 0 42
ISNS(+), ISNS(-) Average current sense common mode range 0 55
TJ Operating temperature range(2) –40 125 °C
Fsw Operating frequency range 100 600 kHz
(1) Recommended Operating Conditions are conditions under the device is intended to be functional. For specifications and test conditions, see Electrical Characteristics .
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

7.4 Thermal Information

THERMAL METRIC(1) LM5175 UNIT
HTSSOP QFN
28 PINS 28 PINS
RθJA Junction-to-ambient thermal resistance 33.1 34.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 17.7 26.6
RθJB Junction-to-board thermal resistance 14.9 6.3
ψJT Junction-to-top characterization parameter 0.4 0.3
ψJB Junction-to-board characterization parameter 14.7 6.2
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.1 2.0
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 125°C junction temperature range unless otherwise stated. VIN = 24 V unless otherwise stated.(1)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN)
VIN Operating input voltage 3.5 42 V
IQ VIN shutdown current VEN/UVLO = 0 V 1.4 10 µA
VIN standby current VEN/UVLO = 1.1 V, non-switching 0.7 2
VIN operating current VEN/UVLO = 2 V, VFB = 0.9 V 1.65 4 mA
VCC
VVCC(VIN) Regulation voltage VBIAS = 0 V, VCC open 6.95 7.35 7.88 V
VUV(VCC) VCC Undervoltage lockout VCC increasing 3.11 3.27 3.43
Undervoltage hysteresis 160 mV
IVCC VCC current limit VVCC = 0 V 65 mA
ROUT(VCC) VCC regulator output impedance IVCC = 30 mA, VIN = 3.5 V 9.3 16 Ω
BIAS
VBIAS(SW) BIAS switchover voltage VIN = 24 V 7.25 8 8.75 V
EN/UVLO
VEN(STBY) Standby threshold EN/UVLO rising 0.55 0.79 0.97 V
IEN(STBY) Standby source current VEN/UVLO = 1.1 V 1 2 3 µA
VEN(OP) Operating threshold EN/UVLO rising 1.17 1.23 1.29 V
ΔIHYS(OP) Operating hysteresis current VEN/UVLO = 2.4 V 1.5 3.5 5.5 µA
SS
ISS Soft-start pull up current VSS = 0 V 4.30 5.65 7.25 µA
VSS(CL) SS clamp voltage SS open 1.27 V
VFB - VSS FB to SS offset VSS = 0 V -15 mV
EA (ERROR AMPLIFIER)
VREF Feedback reference voltage FB = COMP 0.788 0.800 0.812 V
gmEA Error amplifier gm 1.27 mS
ISINK/ISOURCE COMP sink/source current VFB=VREF ± 300 mV 280 µA
ROUT Amplifier output resistance 20 MΩ
BW Unity gain bandwidth 2 MHz
IBIAS(FB) Feedback pin input bias current FB in regulation 100 nA
FREQUENCY
fSW(1) Switching Frequency 1 RT = 133 kΩ 180 200 220 kHz
fSW(2) Switching Frequency 2 RT = 47 kΩ 430 500 565
DITHER
IDITHER Dither source/sink current 10.5 µA
VDITHER Dither high threshold 1.27 V
Dither low threshold 1.16
SYNC
VSYNC Sync input high threshold 2.1 V
Sync input low threshold 1.2
PWSYNC Sync input pulse width 75 500 ns
CURRENT LIMIT
VCS(BUCK) Buck current limit threshold (Valley) VIN = VVISNS = 24 V, VVOSNS = 12 V, VSLOPE = 0 V, TJ = 25°C 53.2 76 98 mV
VCS(BOOST) Boost current limit threshold (Peak) VIN = VVISNS = 12 V, VVOSNS = 18 V, VSLOPE = 0 V, TJ = 25°C 119 170 221
IBIAS(CS/CSG) CS/CSG pin bias current VCS = VCSG = 0 V -75 µA
IOFFSET(CS/CSG) CSG pin bias current VCS = VCSG = 0 V 14
CONSTANT CURRENT LOOP
VSNS Average current loop regulation target VISNS(-) = 24 V, sweep ISNS(+), VSS = 0.8 V 43 50 57 mV
ISNS ISNS(+)/ISNS(–) pin bias currents VISNS(+) = VISNS(–) = VIN = 24 V 7 µA
Gm gm of soft-start pull down amplifier VISNS(+)–VISNS(–) = 55 mV, VSS = 0.5 V 1 mS
SLOPE
ISLOPE Buck adaptive slope current VIN = VVINSNS = 24 V, VVOSNS = 12 V, VSLOPE = 0 V 24 30 35 µA
Boost adaptive slope current VIN = VVINSNS = 12 V, VVOSNS = 18 V, VSLOPE = 0 V 13 17 21
gmSLOPE Slope compensation amplifier gm 2 µS
MODE
IMODE Source current out of MODE pin 17 20 23 µA
VDCM_HIC DCM with hiccup threshold 0.60 0.7 0.76 V
VCCM_HIC CCM with hiccup threshold 1.18 1.28 1.38
VCCM CCM no hiccup threshold 2.22 2.4 2.6
PGOOD
VPGD PGOOD trip threshold for falling FB Measured with respect to VREF –9 %
PGOOD trip threshold for rising FB Measured with respect to VREF 10 %
Hysteresis 1.6 %
ILEAK(PGD) PGOOD leakage current 100 nA
ISINK(PGD) PGOOD sink current VPGOOD = 0.4 V 2 4.2 6.5 mA
OUTPUT OVP
VOVP Output overvoltage threshold At the FB pin 0.86 V
Hysteresis 21 mV
NMOS DRIVERS
IHDRV1,2 Driver peak source current VBOOT - VSW = 7 V 1.8 A
Driver peak sink current VBOOT - VSW = 7 V 2.2
ILDRV1,2 Driver peak source current 1.8
Driver peak sink current 2.2
RHDRV1,2 Driver pull up resistance VBOOT - VSW = 7 V 1.9 Ω
Driver pull down resistance VBOOT - VSW = 7 V 1.3
VUV(BOOT1,2) BOOT1,2 to SW1,2 UVLO threshold HDRV1,2 shut off 2.73 V
BOOT1,2 to SW1,2 UVLO hysteresis HDRV1,2 start switching 280 mV
BOOT1,2 to SW1,2 threshold for refresh pulse 4.45 V
RLDRV1,2 Driver pull up resistance IDRV1,2 = 0.1 A 2 Ω
Driver pull down resistance IDRV1,2 = 0.1 A 1.5
tDT1 Dead time HDRV1,2 off to LDRV1,2 on 55 ns
tDT2 Dead time LDRV1,2 off to HDRV1,2 on 55
THERMAL SHUTDOWN
TSD Thermal shutdown temperature 165 °C
TSD(HYS) Thermal shutdown hysteresis 15
(1) All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

7.6 Typical Characteristics

At TA = 25°C, unless otherwise stated.
LM5175 D009_SNVA37.gif
VOUT=12 V Fsw=300 kHz L1=4.7 μH
IOUT=3 A
Figure 1. Efficiency vs VIN
LM5175 D004_snva37.gif
Figure 3. Oscillator Frequency
LM5175 D006_snva37.gif
Figure 5. IIN Standby
LM5175 D010_SNVA37.gif
Figure 7. IIN Shutdown vs VIN
LM5175 D012_SNVA37.gif
Figure 9. Buck Current Limit vs Temperature
LM5175 D014_SNVA37.gif
Figure 11. VREF vs Temperature
LM5175 fccm_boost.gif
VOUT=12 V VIN=6 V
Figure 13. Forced CCM Operation (Boost)
LM5175 loadtr24vin_2a_4a.gif
VIN=24 V VOUT=12 V Load 2A to 4A
Figure 15. Load Step (Buck)
LM5175 loadtr12vin_2a_4a.gif
VIN=12 V VOUT=12 V Load 2A to 4A
Figure 17. Load Step (Buck-Boost)
LM5175 hiccup_mode.gif
VIN=24 V VOUT=12 V Hiccup Enabled
Figure 19. Hiccup Mode Current Limit
LM5175 D008_SNVA37.gif
VOUT =12 V Fsw=300 kHz L1=4.7 μH
Figure 2. Efficiency vs Load
LM5175 D002_SNVSA37.gif
Figure 4. VCC vs VIN
LM5175 D007_snva37.gif
Figure 6. IIN Operating vs VIN
LM5175 D013_SNVA37.gif
Figure 8. ENABLE/UVLO Rising Threshold vs Temperature
LM5175 D011_SNVA37.gif
Figure 10. Boost Current Limit vs Temperature
LM5175 fccm_buck.gif
VOUT=12 V VIN=24 V
Figure 12. Forced CCM Operation (Buck)
LM5175 fccm_buckboost.gif
VOUT=12 V VIN=12 V
Figure 14. Forced CCM Operation (Buck-Boost)
LM5175 loadtr6vin_2a_4a.gif
VIN=6 V VOUT=12 V Load 2A to 4A
Figure 16. Load Step (Boost)
LM5175 linetr8v_24v_1a.gif
VIN=8 V to 24 V VOUT=12 V IOUT=1A
Figure 18. Line Transient

 
Texas Instruments

© Copyright 1995-2025 Texas Instruments Incorporated. All rights reserved.
Submit documentation feedback | IMPORTANT NOTICE | Trademarks | Privacy policy | Cookie policy | Terms of use | Terms of sale