SLVSI23A
September 2025 – December 2025
DRV81646
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specification
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Timing Requirements
13
5.7
Typical Characteristics
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
Control Interface and Slew Rate (RSLEW/CNTL)
6.3.2
Current Sensing With FET Source Terminals
6.3.3
Integrated Clamp Diode, VCLAMP
6.3.4
Protection Circuits
6.3.4.1
ILIM Analog Current Limit
6.3.4.1.1
Effect of Load Resistance on Power Dissipation Before TSD
6.3.4.2
Cut-Off Delay (COD)
6.3.4.3
INRUSH Mode
6.3.4.4
Thermal Shutdown (TSD)
6.3.4.5
Undervoltage Lockout (UVLO)
6.3.5
Fault Conditions Summary
6.4
Device Functional Modes
6.4.1
Hardware Interface Operation
6.4.2
Parallel Outputs
6.4.3
SPI Mode
6.4.3.1
Parity Bit Calculation
6.4.3.2
SPI Input Packet
6.4.3.3
SPI Response Packet
6.4.3.4
SPI Error Reporting
6.4.3.5
SPI Daisy Chain
7
Application and Implementation
7.1
Application Information
7.2
Typical Application
7.2.1
External Components
7.2.2
Continuous Current Capability
7.2.3
Power Dissipation
7.2.4
Application Curves
7.3
Power Supply Recommendations
7.3.1
Bulk Capacitance
7.4
Layout
7.4.1
Layout Guidelines
7.4.2
Layout Example
8
Device and Documentation Support
8.1
Documentation Support
8.1.1
Related Documentation
8.2
Receiving Notification of Documentation Updates
8.3
Support Resources
8.4
Trademarks
8.5
Electrostatic Discharge Caution
8.6
Glossary
9
Revision History
10
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
PWP|20
MHTS001H
DGQ|24
MPSS215
サーマルパッド・メカニカル・データ
PWP|20
QFND862
発注情報
slvsi23a_oa
Data Sheet
DRV81646
:
65V Four-Channel Low-side Driver with Hardware, SPI, and Configurable Slew Rate and Cut-off Duration