SPRSPB5A
December 2024 – May 2025
AM62D-Q1
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
3.1
Functional Block Diagram
4
Device Comparison
4.1
Related Products
5
Terminal Configuration and Functions
5.1
Pin Diagrams
5.2
Pin Attributes
11
12
5.3
Signal Descriptions
14
5.3.1
CPSW3G
5.3.1.1
MAIN Domain
17
18
19
20
5.3.2
CPTS
5.3.2.1
MAIN Domain
23
5.3.3
CSI-2
5.3.3.1
MAIN Domain
26
5.3.4
DDRSS
5.3.4.1
MAIN Domain
29
5.3.5
ECAP
5.3.5.1
MAIN Domain
32
33
34
5.3.6
Emulation and Debug
5.3.6.1
MAIN Domain
37
5.3.6.2
MCU Domain
39
5.3.7
EPWM
5.3.7.1
MAIN Domain
42
43
44
45
5.3.8
EQEP
5.3.8.1
MAIN Domain
48
49
50
5.3.9
GPIO
5.3.9.1
MAIN Domain
53
54
5.3.9.2
MCU Domain
56
5.3.10
GPMC
5.3.10.1
MAIN Domain
59
5.3.11
I2C
5.3.11.1
MAIN Domain
62
63
64
65
5.3.11.2
MCU Domain
67
5.3.11.3
WKUP Domain
69
5.3.12
MCAN
5.3.12.1
MAIN Domain
72
5.3.12.2
MCU Domain
74
75
5.3.13
MCASP
5.3.13.1
MAIN Domain
78
79
80
5.3.14
MCSPI
5.3.14.1
MAIN Domain
83
84
85
5.3.14.2
MCU Domain
87
88
5.3.15
MDIO
5.3.15.1
MAIN Domain
91
5.3.16
MMC
5.3.16.1
MAIN Domain
94
95
96
5.3.17
OSPI
5.3.17.1
MAIN Domain
99
5.3.18
Power Supply
101
5.3.19
Reserved
103
5.3.20
System and Miscellaneous
5.3.20.1
Boot Mode Configuration
5.3.20.1.1
MAIN Domain
107
5.3.20.2
Clock
5.3.20.2.1
MCU Domain
110
5.3.20.2.2
WKUP Domain
112
5.3.20.3
System
5.3.20.3.1
MAIN Domain
115
5.3.20.3.2
MCU Domain
117
5.3.20.3.3
WKUP Domain
119
5.3.20.4
VMON
121
5.3.21
TIMER
5.3.21.1
MAIN Domain
124
5.3.21.2
MCU Domain
126
5.3.21.3
WKUP Domain
128
5.3.22
UART
5.3.22.1
MAIN Domain
131
132
133
134
135
136
137
5.3.22.2
MCU Domain
139
5.3.22.3
WKUP Domain
141
5.3.23
USB
5.3.23.1
MAIN Domain
144
145
5.4
Pin Connectivity Requirements
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings for Devices which are not AEC - Q100 Qualified
6.3
ESD Ratings for AEC - Q100 Qualified Devices
6.4
Power-On Hours (POH)
6.5
Recommended Operating Conditions
6.6
Operating Performance Points
6.7
Power Consumption Summary
6.8
Electrical Characteristics
6.8.1
I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics
6.8.2
Fail-Safe Reset (FS RESET) Electrical Characteristics
6.8.3
High-Frequency Oscillator (HFOSC) Electrical Characteristics
6.8.4
Low-Frequency Oscillator (LFXOSC) Electrical Characteristics
6.8.5
SDIO Electrical Characteristics
6.8.6
LVCMOS Electrical Characteristics
6.8.7
CSI-2 (D-PHY) Electrical Characteristics
6.8.8
USB2PHY Electrical Characteristics
6.8.9
DDR Electrical Characteristics
6.9
VPP Specifications for One-Time Programmable (OTP) eFuses
6.9.1
Recommended Operating Conditions for OTP eFuse Programming
6.9.2
Hardware Requirements
6.9.3
Programming Sequence
6.9.4
Impact to Your Hardware Warranty
6.10
Thermal Resistance Characteristics
6.10.1
Thermal Resistance Characteristics for ANF Package
6.11
Temperature Sensor Characteristics
6.12
Timing and Switching Characteristics
6.12.1
Timing Parameters and Information
6.12.2
Power Supply Requirements
6.12.2.1
Power Supply Slew Rate Requirement
6.12.2.2
Power Supply Sequencing
6.12.2.2.1
Power-Up Sequencing
6.12.2.2.2
Power-Down Sequencing
6.12.2.2.3
Partial IO Power Sequencing
6.12.3
System Timing
6.12.3.1
Reset Timing
6.12.3.2
Error Signal Timing
6.12.3.3
Clock Timing
6.12.4
Clock Specifications
6.12.4.1
Input Clocks / Oscillators
6.12.4.1.1
MCU_OSC0 Internal Oscillator Clock Source
6.12.4.1.2
MCU_OSC0 LVCMOS Digital Clock Source
6.12.4.1.3
WKUP_LFOSC0 Internal Oscillator Clock Source
6.12.4.1.4
WKUP_LFOSC0 LVCMOS Digital Clock Source
6.12.4.1.5
WKUP_LFOSC0 Not Used
6.12.4.2
Output Clocks
6.12.4.3
PLLs
6.12.4.4
Recommended System Precautions for Clock and Control Signal Transitions
6.12.5
Peripherals
6.12.5.1
CPSW3G
6.12.5.1.1
CPSW3G MDIO Timing
6.12.5.1.2
CPSW3G RMII Timing
6.12.5.1.3
CPSW3G RGMII Timing
6.12.5.2
CPTS
6.12.5.3
CSI-2
6.12.5.4
DDRSS
6.12.5.5
ECAP
6.12.5.6
Emulation and Debug
6.12.5.6.1
Trace
6.12.5.6.2
JTAG
6.12.5.7
EPWM
6.12.5.8
EQEP
6.12.5.9
GPIO
6.12.5.10
GPMC
6.12.5.10.1
GPMC and NOR Flash — Synchronous Mode
6.12.5.10.2
GPMC and NOR Flash — Asynchronous Mode
6.12.5.10.3
GPMC and NAND Flash — Asynchronous Mode
6.12.5.11
I2C
6.12.5.12
MCAN
6.12.5.13
MCASP
6.12.5.14
MCSPI
6.12.5.14.1
MCSPI — Controller Mode
6.12.5.14.2
MCSPI — Peripheral Mode
6.12.5.15
MMCSD
6.12.5.15.1
MMC0 - eMMC/SD/SDIO Interface
6.12.5.15.1.1
Legacy SDR Mode
6.12.5.15.1.2
High Speed SDR Mode
6.12.5.15.1.3
High Speed DDR Mode
6.12.5.15.1.4
HS200 Mode
6.12.5.15.1.5
Default Speed Mode
6.12.5.15.1.6
High Speed Mode
6.12.5.15.1.7
UHS–I SDR12 Mode
6.12.5.15.1.8
UHS–I SDR25 Mode
6.12.5.15.1.9
UHS–I SDR50 Mode
6.12.5.15.1.10
UHS–I DDR50 Mode
6.12.5.15.1.11
UHS–I SDR104 Mode
6.12.5.15.2
MMC1/MMC2 - SD/SDIO Interface
6.12.5.15.2.1
Default Speed Mode
6.12.5.15.2.2
High Speed Mode
6.12.5.15.2.3
UHS–I SDR12 Mode
6.12.5.15.2.4
UHS–I SDR25 Mode
6.12.5.15.2.5
UHS–I SDR50 Mode
6.12.5.15.2.6
UHS–I DDR50 Mode
6.12.5.15.2.7
UHS–I SDR104 Mode
6.12.5.16
OSPI
6.12.5.16.1
OSPI0 PHY Mode
6.12.5.16.1.1
OSPI0 With PHY Data Training
6.12.5.16.1.2
OSPI0 Without Data Training
6.12.5.16.1.2.1
OSPI0 PHY SDR Timing
6.12.5.16.1.2.2
OSPI0 PHY DDR Timing
6.12.5.16.2
OSPI0 Tap Mode
6.12.5.16.2.1
OSPI0 Tap SDR Timing
6.12.5.16.2.2
OSPI0 Tap DDR Timing
6.12.5.17
Timers
6.12.5.18
UART
6.12.5.19
USB
7
Detailed Description
7.1
Overview
7.2
Processor Subsystems
7.2.1
Arm Cortex-A53 Subsystem
7.2.2
Device/Power Manager
7.2.3
MCU Arm Cortex-R5F Subsystem
7.3
Accelerators and Coprocessors
7.3.1
C7x256V DSP with Matrix Multiplication Accelerator
7.4
Other Subsystems
7.4.1
Dual Clock Comparator (DCC)
7.4.2
Data Movement Subsystem (DMSS)
7.4.3
Memory Cyclic Redundancy Check (MCRC)
7.4.4
Peripheral DMA Controller (PDMA)
7.4.5
Real-Time Clock (RTC)
7.5
Peripherals
7.5.1
Gigabit Ethernet Switch (CPSW3G)
7.5.2
Camera Serial Interface Receiver (CSI_RX_IF)
7.5.3
Enhanced Capture (ECAP)
7.5.4
Error Location Module (ELM)
7.5.5
Enhanced Pulse Width Modulation (EPWM)
7.5.6
Error Signaling Module (ESM)
7.5.7
Enhanced Quadrature Encoder Pulse (EQEP)
7.5.8
General-Purpose Interface (GPIO)
7.5.9
General-Purpose Memory Controller (GPMC)
7.5.10
Global Timebase Counter (GTC)
7.5.11
Inter-Integrated Circuit (I2C)
7.5.12
Modular Controller Area Network (MCAN)
7.5.13
Multichannel Audio Serial Port (MCASP)
7.5.14
Multichannel Serial Peripheral Interface (MCSPI)
7.5.15
Multi-Media Card Secure Digital (MMCSD)
7.5.16
Octal Serial Peripheral Interface (OSPI)
7.5.17
Timers
7.5.18
Universal Asynchronous Receiver/Transmitter (UART)
7.5.19
Universal Serial Bus Subsystem (USBSS)
8
Applications, Implementation, and Layout
8.1
Device Connection and Layout Fundamentals
8.1.1
Power Supply
8.1.1.1
Power Distribution Network Implementation Guidance
8.1.2
External Oscillator
8.1.3
JTAG, EMU, and TRACE
8.1.4
Unused Pins
8.2
Peripheral- and Interface-Specific Design Information
8.2.1
DDR Board Design and Layout Guidelines
8.2.2
OSPI/QSPI/SPI Board Design and Layout Guidelines
8.2.2.1
No Loopback, Internal PHY Loopback, and Internal Pad Loopback
8.2.2.2
External Board Loopback
8.2.2.3
DQS (only available in Octal SPI devices)
8.2.3
USB VBUS Design Guidelines
8.2.4
System Power Supply Monitor Design Guidelines
8.2.5
High Speed Differential Signal Routing Guidance
8.2.6
Thermal Solution Guidance
8.3
Clock Routing Guidelines
8.3.1
Oscillator Routing
9
Device and Documentation Support
9.1
Device Nomenclature
9.1.1
Standard Package Symbolization
9.1.2
Device Naming Convention
9.2
Tools and Software
9.3
Documentation Support
9.4
Support Resources
9.5
Trademarks
9.6
Electrostatic Discharge Caution
9.7
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
11.1
Packaging Information
パッケージ・オプション
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ(パッケージ|ピン)
ANF|484
サーマルパッド・メカニカル・データ
発注情報
sprspb5a_oa
sprspb5a_pm
Data Sheet
AM62Dx Sitara™ Processors