ADS7057 14 位，2.5 MSPS，差分输入，小型低功耗 SAR ADC

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1 特性

2.5 MSPS 吞吐量
封装尺寸小：
- X2QFN-8 封装 (1.5mm × 1.5mm)
全差动输入范围：±AVDD
宽工作电压范围：
- AVDD：2.35V 至 3.6V
- DVDD：1.65V 至 3.6V（与 AVDD 无关）
- 温度范围：-40°C 至 +125°C
性能优异：
- 14 位 NMC DNL，±0.9-LSB INL
- 79.5dB SINAD（2kHz 时）
- 77dB SINAD（1MHz 时）
低功耗：
- 3.6mW（2.5 MSPS，3.3V AVDD 时）
- 160µW（100kSPS，3.3V AVDD 时）
- 82µW（100kSPS，2.5V AVDD 时）
集成失调电压校准
与 SPI 兼容的串行接口：60MHz
符合 JESD8-7A 标准的数字 I/O

2 应用

光学编码器
声纳接收器
探鱼器
I/Q 解调器
光线路卡和模块
热成像摄像机
超声波流量计
手持无线电

3 说明

ADS7057 器件属于引脚对引脚兼容的高速低功耗、单通道逐次逼近型寄存器 (SAR) 类型的模数转换器 (ADC) 系列。该器件系列包含多个分辨率、吞吐量和模拟输入型号（有关器件列表，请参阅表格1）。

ADS7057 是一款 14 位 2.5 MSPS SAR ADC，支持±AVDD 范围内的全差分输入，AVDD 的范围为2.35V 至 3.6V。

内部失调电压校准功能在整个 AVDD 和工作温度范围内可保持优异的失调电压规格。

该器件支持由 CS 和 SCLK 信号控制的兼容 SPI 的串行接口。输入信号通过 CS 下降沿进行采样，而 SCLK 用于转换和串行数据输出。该器件支持宽数字电源范围（1.65V 至 3.6V），可直接连接到各种主机控制器。ADS7057 的标称 DVDD 范围（1.65V 至 1.95V）符合 JESD8-7A 标准。

ADS7057 采用 8 引脚小型 X2QFN 封装，可以在广泛的工业温度范围（–40°C 至 +125°C）内正常工作。该器件体积小巧，功耗极低，非常适合需要高速高分辨率数据采集的空间受限型电池供电应用。

器件信息⁽¹⁾

部件名称	封装	封装尺寸（标称值）
ADS7057	X2QFN (8)	1.50mm x 1.50mm

如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。

典型应用

4 修订历史记录

日期	修订版本	说明
2017 年 12 月	*	初始发行版

5 Pin Configuration and Functions

RUG Package

8-Pin X2QFN

Top View

Pin Functions

PIN		I/O	DESCRIPTION
NO.	NAME	I/O	DESCRIPTION
1	CS	Digital input	Chip-select signal, active low
2	SDO	Digital output	Serial data out
3	SCLK	Digital input	Serial clock
4	DVDD	Supply	Digital I/O supply voltage
5	GND	Supply	Ground for power supply, all analog and digital signals are referred to this pin
6	AVDD	Supply	Analog power-supply input, also provides the reference voltage to the ADC
7	AINP	Analog input	Analog signal input, positive
8	AINM	Analog input	Analog signal input, negative

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

	MIN	MAX	UNIT
AVDD to GND	–0.3	3.9	V
DVDD to GND	–0.3	3.9	V
AINP to GND	–0.3	AVDD + 0.3	V
AINM to GND	–0.3	AVDD + 0.3	V
Input current to any pin except supply pins	–10	10	mA
Digital input voltage to GND	–0.3	DVDD + 0.3	V
Storage temperature, T_stg	–60	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
AVDD	Analog supply voltage range	2.35	3.3	3.6	V
DVDD	Digital supply voltage range	1.65	1.8	3.6	V
T_A	Operating free-air temperature	–40	25	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		ADS7057	UNIT
		RUG (X2QFN)
		8 PINS
R_θJA	Junction-to-ambient thermal resistance	177.5	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	51.5	°C/W
R_θJB	Junction-to-board thermal resistance	76.7	°C/W
ψ_JT	Junction-to-top characterization parameter	1	°C/W
ψ_JB	Junction-to-board characterization parameter	76.7	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	N/A	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

at AVDD = 3.3 V, DVDD = 1.65 V to 3.6 V, f_sample = 2.5 MSPS, and V_CM = 1.65 V (unless otherwise noted); minimum and maximum values for T_A = –40°C to +125°C; typical values at T_A = 25°C

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ANALOG INPUT
	Full-scale input voltage span⁽¹⁾		–AVDD		AVDD	V
	Absolute input voltage range	AINP to GND	–0.1		AVDD + 0.1	V
	Absolute input voltage range	AINM to GND	–0.1		AVDD + 0.1	V
	Common-mode voltage	(AINP + AINM) / 2	(AVDD / 2) – 0.1	(AVDD / 2) + 0.1		V
C_S	Sampling capacitance			16		pF
SYSTEM PERFORMANCE
	Resolution			14		Bits
NMC	No missing codes		14			Bits
INL⁽⁸⁾	Integral nonlinearity		–3	±0.9	3	LSB⁽²⁾
DNL	Differential nonlinearity		–0.99	±0.3	1	LSB
E_O⁽⁸⁾	Offset error	After calibration⁽⁷⁾	–6	±1	6	LSB
dV_OS/dT	Offset error drift with temperature			1.75		ppm/°C
E_G⁽⁸⁾	Gain error		–0.1	±0.01	0.1	%FS
	Gain error drift with temperature			0.5		ppm/°C
SAMPLING DYNAMICS
t_CONV	Conversion time			18 × t_SCLK		ns
t_ACQ	Acquisition time		95			ns
f_SAMPLE	Maximum throughput rate	60-MHz SCLK, AVDD = 2.35 V to 3.6 V			2.5	MHz
	Aperture delay			3		ns
	Aperture jitter, RMS			12		ps
DYNAMIC CHARACTERISTICS
SNR	Signal-to-noise ratio⁽⁴⁾	AVDD = 3.3 V, f_IN = 2 kHz	76	79.6		dB
SNR	Signal-to-noise ratio⁽⁴⁾	AVDD = 2.5 V, f_IN = 2 kHz		78.5		dB
THD	Total harmonic distortion⁽⁴⁾⁽³⁾	f_IN = 2 kHz		–92		dB
		f_IN = 500 kHz		–90.4
		f_IN = 1000 kHz		–90.3
SINAD	Signal-to-noise and distortion⁽⁴⁾	f_IN = 2 kHz	76	79.3		dB
		f_IN = 500 kHz		78.1
		f_IN = 1000 kHz		77.1
SFDR	Spurious-free dynamic range⁽⁴⁾	f_IN = 2 kHz		95		dB
		f_IN = 500 kHz		93.4
		f_IN = 1000 kHz		92.4
BW_(fp)	Full-power bandwidth	At –3 dB		200		MHz
DIGITAL INPUT/OUTPUT (CMOS Logic Family)
V_IH	High-level input voltage⁽⁵⁾		0.65 DVDD		DVDD + 0.3	V
V_IL	Low-level input voltage⁽⁵⁾		–0.3		0.35 DVDD	V
V_OH	High-level output voltage⁽⁵⁾	At I_source = 500 µA	0.8 DVDD		DVDD	V
V_OH	High-level output voltage⁽⁵⁾	At I_source = 2 mA	DVDD – 0.45		DVDD	V
V_OL	Low-level output voltage⁽⁵⁾	At I_sink = 500 µA	0		0.2 DVDD	V
V_OL	Low-level output voltage⁽⁵⁾	At I_sink = 2 mA	0		0.45	V
POWER-SUPPLY REQUIREMENTS
AVDD	Analog supply voltage		2.35	3	3.6	V
DVDD	Digital I/O supply voltage		1.65	3	3.6	V
I_AVDD	Analog supply current	AVDD = 3.3 V, f_SAMPLE = 2.5 MSPS		1100	1400	µA
		AVDD = 3.3 V, f_SAMPLE = 100 kSPS		47	56
		AVDD = 3.3 V, f_SAMPLE = 10 kSPS		5
		AVDD = 2.5 V, f_SAMPLE = 2.5 MSPS		820
		Static current with CS and SCLK high		0.02
I_DVDD	Digital supply current	DVDD = 1.8 V, CSDO = 20 pF, output code = 2AAAh⁽⁶⁾		630		µA
I_DVDD	Digital supply current	DVDD = 1.8 V, static current with CS and SCLK high		0.01		µA

(1) Ideal input span; does not include gain or offset error.

(2) LSB means least significant bit.

(3) Calculated on the first nine harmonics of the input frequency.

(4) All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full-scale, unless otherwise noted.

(5) Digital voltage levels comply with the JESD8-7A standard for DVDD from 1.65 V to 1.95 V; see the Parameter Measurement Information section for details.

(6) See the Estimating Digital Power Consumption section for details.

(7) See the OFFCAL State section for details.

(8) See Figure 31, Figure 29, and Figure 30 for statistical distribution data for INL, offset error, and gain error.

6.6 Timing Requirements

all specifications are at AVDD = 2.35 V to 3.6 V, DVDD = 1.65 V to 3.6 V, and C_LOAD-SDO = 20 pF (unless otherwise noted); minimum and maximum values for T_A = –40°C to +125°C; typical values at T_A = 25°C

		MIN	MAX	UNIT
t_CLK	Time period of SCLK	16.66		ns
t_{su_CSCK}	Setup time: CS falling edge to SCLK falling edge	7		ns
t_{ht_CKCS}	Hold time: SCLK rising edge to CS rising edge	8		ns
t_{ph_CK}	SCLK high time	0.45	0.55	t_SCLK
t_{pl_CK}	SCLK low time	0.45	0.55	t_SCLK
t_{ph_CS}	CS high time	15		ns

6.7 Switching Characteristics

PARAMETER		MIN	TYP	MAX	UNIT
t_CYCLE⁽¹⁾	Cycle time	400			ns
t_CONV	Conversion time		18 × t_SCLK		ns
t_{den_CSDO}	Delay time: CS falling edge to data enable			6.5	ns
t_{d_CKDO}	Delay time: SCLK rising edge to (next) data valid on SDO			10	ns
t_{ht_CKDO}	SCLK rising edge to current data invalid	2.5			ns
t_{dz_CSDO}	Delay time: CS rising edge to SDO going to tri-state	5.5			ns