ADC32RF42 双通道 14 位 1.5GSPS 模数转换器
- ZHCSG95 May 2017 ADC32RF42
  
  PRODUCTION DATA.

Full reading width

DATA SHEET

ADC32RF42 双通道 14 位 1.5GSPS 模数转换器

本资源的原文使用英文撰写。为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

14 位双通道 1.5GSPS ADC
本底噪声：–151.8dBFS/Hz
射频输入支持的频率最高可达 4GHz
孔径抖动：90f_s
通道隔离：f_IN = 1.8GHz 时为 95dB
频谱性能（f_IN = 950MHz，–2dBFS）：
- SNR：61.1dBFS
- SFDR：67dBc（HD2、HD3）
频谱性能（f_IN = 1.85GHz，–2dBFS）：
- 信噪比 (SNR)：58.9dBFS
- SFDR：64dBc（HD2、HD3）
片上数字下变频器：
- 最多 4 个下变频器 (DDC)（双频带模式）
- 每个 DDC 最多配有 3 个独立数控振荡器 (NCO)
提供过压保护的片上输入钳位
用于 AGC 支持的带警报引脚的可编程片上功率检测器
片上抖动
片上输入端接电阻
输入满量程：1.35 V_PP
支持多芯片同步
JESD204B 接口：
- 基于子类 1 的确定性延迟
- 每通道 4 条信道，高达 12.5Gbps
功率耗散：1.5GSPS 时为 2W/通道
72 引脚超薄型四方扁平无引线 (VQFN) 封装 (10mm × 10mm)

2 应用

多频带、多模式 2G、3G、4G 蜂窝接收器
相控阵列雷达
电子对抗战
线缆基础设施
无线宽带
高速数字转换器
软件定义无线电
通信测试设备
微波和毫米波接收器

3 说明

ADC32RF42 器件是一款 14 位 1.5GSPS 双通道模数转换器 (ADC)，支持输入频率高达 4GHz 及以上的射频采样。ADC32RF42 专为高信噪比 (SNR) 设计，其噪声频谱密度为 –151.8dBFS/Hz，并可在较大输入频率范围提供动态范围和通道隔离。经缓冲的模拟输入配有片上端接电阻，可在较宽频率范围内提供统一输入阻抗并最大程度地降低采样和保持毛刺脉冲能量。

每个 ADC 通道均可连接到一个双频带数字下变频器 (DDC)，每个 DDC 最多连接三个独立的 16 位数控振荡器 (NCO) 用于相位相干跳频。此外，ADC 还配有前端峰值和 RMS 功率检测器及报警功能，用以支持外部自动增益控制 (AGC) 算法。

ADC32RF42 支持具有基于子类 1 确定性延迟的 JESD204B 串行接口，其数据速率高达 12.5Gbps，每个 ADC 最多具有四条信道。该器件采用 72 引脚 VQFN 封装 (10mm × 10mm)，支持工业级温度范围（-40℃ 至 +85°C）。

器件信息⁽¹⁾

器件型号	封装	封装尺寸（标称值）
ADC32RF42	VQFN (72)	10.00mm x 10.00mm

要了解所有可用封装，请参见数据表末尾的可订购产品附录。

简化框图

4 修订历史记录

日期	修订版本	注释
2017 年 5 月	*	首次发布。

5 Device Family Comparison Table

PART NUMBER	SPEED GRADE (MSPS)	RESOLUTION (Bits)	CHANNELS
ADC32RF45	3000	14	2
ADC32RF44	2600	14	2
ADC32RF42	1500	14	2

6 Pin Configuration and Functions

RMP Package

72-Pin VQFN

Top View

Pin Functions

NAME	NO.	I/O	DESCRIPTION
INPUT, REFERENCE
INAM	41	I	Differential analog input for channel A
INAP	42	I	Differential analog input for channel A
INBM	14	I	Differential analog input for channel B
INBP	13	I	Differential analog input for channel B
CM	22	O	Common-mode voltage for analog inputs, 1.2 V
CLOCK, SYNC
CLKINM	28	I	Differential clock input for the analog-to-digital converter (ADC). This pin has an internal differential 100-Ω termination.
CLKINP	27	I
SYSREFM	34	I	External sync input. This pin has an internal, differential 100-Ω termination and requires external biasing.
SYSREFP	33	I
GPIO1	19	I/O	GPIO control pin; configured through the SPI. This pin can be configured to be either a fast overrange output for channel A and B, a fast detect alarm signal from the peak power detect, or a numerically-controlled oscillator (NCO) control. GPIO 4 (pin 63) can also be configured as a single-ended SYNCB input.
GPIO2	20
GPIO3	21
GPIO4	63
CONTROL, SERIAL
RESET	48	I	Hardware reset; active high. This pin has an internal 20-kΩ pulldown resistor.
SCLK	6	I	Serial interface clock input. This pin has an internal 20-kΩ pulldown resistor.
SDIN	5	I/O	Serial interface data input. This pin has an internal 20-kΩ pulldown resistor. SDIN can be data input in 4-wire mode, data input and output in 3-wire mode.
SEN	7	I	Serial interface enable. This pin has an internal 20-kΩ pullup resistor to DVDD.
SDOUT	11	O	Serial interface data output in 4-wire mode
PDN	50	I	Power down; active high. This pin can be configured through an SPI register setting and can be configured to a fast overrange output channel B through the SPI. This pin has an internal 20-kΩ pulldown resistor.
DATA INTERFACE
DA0M	62	O	JESD204B serial data output for channel A
DA0P	61
DA1M	59
DA1P	58
DA2M	56
DA2P	55
DA3M	54
DA3P	53
DB0M	65	O	JESD204B serial data output for channel B
DB0P	66
DB1M	68
DB1P	69
DB2M	71
DB2P	72
DB3M	1
DB3P	2
SYNCBM	36	I	Synchronization input for the JESD204B port. This pin has an LVDS or 1.8-V logic input, an optional on-chip 100-Ω termination, and is selectable through the SPI. This pin requires external biasing.
SYNCBP	35	I
POWER SUPPLY
AVDD19	10, 16, 24, 31, 39, 45	I	Analog 1.9-V power supply
AVDD	9, 12, 15, 17, 25, 30, 38, 40, 43, 44, 46	I	Analog 1.15-V power supply
DVDD	4, 8, 47, 51, 57, 64, 70	I	Digital 1.15 V-power supply, including the JESD204B transmitter
GND	3, 18, 23, 26, 29, 32, 37, 49, 52, 60, 67	I	Ground; shorted to thermal pad inside device

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Supply voltage range	AVDD19	–0.3	2.1	V
	AVDD	–0.3	1.4
	DVDD	–0.3	1.4
Voltage applied to input pins	INAP, INAM and INBP, INBM	–0.3	AVDD19 + 0.3	V
	CLKINP, CLKINM	–0.3	AVDD + 0.6
	SYSREFP, SYSREFM, SYNCBP, SYNCBM	–0.3	AVDD + 0.6
	SCLK, SEN, SDIN, RESET, PDN, GPIO1, GPIO2, GPIO3, GPIO4	–0.2	AVDD19 + 0.2
Voltage applied to output pins		–0.3	2.2	V
Temperature	Operating free-air, T_A	–40	85	°C
Temperature	Storage, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±1000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
Supply voltage⁽²⁾	AVDD19	1.8	1.9	2.0	V
	AVDD	1.1	1.15	1.25
	DVDD	1.1	1.15	1.2
Temperature	Operating free-air, T_A	–40		85	°C
Temperature	Operating junction, T_J		105⁽¹⁾	125	°C

(1) Prolonged use above this junction temperature may increase the device failure-in-time (FIT) rate.

(2) Always power up the DVDD supply (1.15 V) before the AVDD19 (1.9 V) supply. The AVDD (1.15 V) supply can come up in any order.

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		ADC32RF42	UNIT
		RMP (VQFN)
		72 PINS
R_θJA	Junction-to-ambient thermal resistance	21.8	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	4.4	°C/W
R_θJB	Junction-to-board thermal resistance	2.0	°C/W
ψ_JT	Junction-to-top characterization parameter	0.1	°C/W
ψ_JB	Junction-to-board characterization parameter	2.0	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	0.2	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and ADC sampling rate = 1.5 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER CONSUMPTION⁽⁴⁾ (Dual-Channel Operation, Both Channels A and B are Active; DDC Bypass Mode⁽³⁾)
I_AVDD19	1.9-V analog supply current	14-bit, bypass mode, f_S = 1.5 GSPS		1150	1969	mA
I_AVDD	1.15-V analog supply current	14-bit, bypass mode, f_S = 1.5 GSPS		604	1079	mA
I_DVDD	1.15-V digital supply current	14-bit, bypass mode, f_S = 1.5 GSPS		1000	1846	mA
P_D	Power dissipation	14-bit, bypass mode, f_S = 1.5 GSPS		4.03	6.95	W
	Global power-down power dissipation			360		mW
ANALOG INPUTS
	Resolution			14		Bits
	Differential input full-scale			1.35		V_PP
V_IC	Input common-mode voltage			1.2⁽⁵⁾		V
R_IN	Input resistance	Differential resistance at dc		65		Ω
C_IN	Input capacitance	Differential capacitance at dc		2		pF
	V_CM common-mode voltage output			1.2		V
	Analog input bandwidth (–3-dB point)	ADC driven with 50-Ω source		3200		MHz
ISOLATION
	Crosstalk isolation between channel A and channel B⁽¹⁾	f_IN = 100 MHz		100		dBc
		f_IN = 900 MHz		99
		f_IN = 1800 MHz		95
		f_IN = 2700 MHz		86
		f_IN = 3500 MHz		85
CLOCK INPUT⁽²⁾
	Input clock frequency		750	1500		MHz
	Differential (peak-to-peak) input clock amplitude		0.5	1.5	2.5	V_PP
	Input clock duty cycle		45%	50%	55%
	Internal clock biasing			1.0		V
	Internal clock termination (differential)			100		Ω

(1) Crosstalk is measured with a –2-dBFS input signal on aggressor channel and no input on the victim channel.

(2) See Figure 32.

(3) Full-scale signal is applied to the analog inputs of all active channels.

(4) See the Power Consumption in Different Modes section for more details.

(5) When used in dc-coupling mode, the common-mode voltage at the analog inputs should be kept within V_CM ±25 mV for best performance.

7.6 AC Performance Characteristics

typical values specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and ADC sampling rate = 1.5 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)

PARAMETER		TEST CONDITIONS	NOM	UNIT
SNR	Signal-to-noise ratio	f_IN = 100 MHz, A_OUT = –2 dBFS	62.8	dBFS
		f_IN = 300 MHz, A_OUT = –2 dBFS	62.6
		f_IN = 950 MHz, A_OUT = –2 dBFS	61.1
		f_IN = 1200 MHz, A_OUT = –2 dBFS	60.4
		f_IN = 1350 MHz, A_OUT = –2 dBFS	60.0
		f_IN = 1850 MHz, A_OUT = –2 dBFS	58.9
		f_IN = 2100 MHz, A_OUT = –2 dBFS	57.9
NSD	Noise spectral density averaged across the Nyquist zone	f_IN = 100 MHz, A_OUT = –2 dBFS	151.6	dBFS/Hz
		f_IN = 300 MHz, A_OUT = –2 dBFS	151.4
		f_IN = 950 MHz, A_OUT = –2 dBFS	149.8
		f_IN = 1200 MHz, A_OUT = –2 dBFS	149.1
		f_IN = 1350 MHz, A_OUT = –2 dBFS	148.8
		f_IN = 1850 MHz, A_OUT = –2 dBFS	147.6
		f_IN = 2100 MHz, A_OUT = –2 dBFS	146.7
	Small-signal SNR	f_IN = 950 MHz, A_OUT = –40 dBFS	63.0	dBFS
NF⁽¹⁾	Input noise figure	f_IN = 950 MHz, A_OUT = –40 dBFS	27.7	dB
SINAD	Signal-to-noise and distortion ratio	f_IN = 100 MHz, A_OUT = –2 dBFS	61.4	dBFS
		f_IN = 300 MHz, A_OUT = –2 dBFS	61.0
		f_IN = 950 MHz, A_OUT = –2 dBFS	60.9
		f_IN = 1200 MHz, A_OUT = –2 dBFS	59.9
		f_IN = 1350 MHz, A_OUT = –2 dBFS	59.2
		f_IN = 1850 MHz, A_OUT = –2 dBFS	58.2
		f_IN = 2100 MHz, A_OUT = –2 dBFS	55.8
ENOB	Effective number of bits	f_IN = 100 MHz, A_OUT = –2 dBFS	9.9	Bits
		f_IN = 300 MHz, A_OUT = –2 dBFS	9.8
		f_IN = 950 MHz, A_OUT = –2 dBFS	9.8
		f_IN = 1200 MHz, A_OUT = –2 dBFS	9.6
		f_IN = 1350 MHz, A_OUT = –2 dBFS	9.5
		f_IN = 1850 MHz, A_OUT = –2 dBFS	9.4
		f_IN = 2100 MHz, A_OUT = –2 dBFS	9.0
SFDR	Spurious-free dynamic range	f_IN = 100 MHz, A_OUT = –2 dBFS	67	dBc
		f_IN = 300 MHz, A_OUT = –2 dBFS	64
		f_IN = 950 MHz, A_OUT = –2 dBFS	70
		f_IN = 1200 MHz, A_OUT = –2 dBFS	67
		f_IN = 1350 MHz, A_OUT = –2 dBFS	66
		f_IN = 1850 MHz, A_OUT = –2 dBFS	64
		f_IN = 2100 MHz, A_OUT = –2 dBFS	58
HD2	Second-order harmonic distortion	f_IN = 100 MHz, A_OUT = –2 dBFS	68	dBc
		f_IN = 300 MHz, A_OUT = –2 dBFS	64
		f_IN = 950 MHz, A_OUT = –2 dBFS	72
		f_IN = 1200 MHz, A_OUT = –2 dBFS	70
		f_IN = 1350 MHz, A_OUT = –2 dBFS	67
		f_IN = 1850 MHz, A_OUT = –2 dBFS	64
		f_IN = 2100 MHz, A_OUT = –2 dBFS	58
HD3	Third-order harmonic distortion	f_IN = 100 MHz, A_OUT = –2 dBFS	67	dBc
		f_IN = 300 MHz, A_OUT = –2 dBFS	71
		f_IN = 950 MHz, A_OUT = –2 dBFS	70
		f_IN = 1200 MHz, A_OUT = –2 dBFS	67
		f_IN = 1350 MHz, A_OUT = –2 dBFS	70
		f_IN = 1850 MHz, A_OUT = –2 dBFS	73
		f_IN = 2100 MHz, A_OUT = –2 dBFS	66
HD4, HD5	Fourth- and fifth-order harmonic distortion	f_IN = 100 MHz, A_OUT = –2 dBFS	89	dBc
		f_IN = 300 MHz, A_OUT = –2 dBFS	84
		f_IN = 950 MHz, A_OUT = –2 dBFS	85
		f_IN = 1200 MHz, A_OUT = –2 dBFS	83
		f_IN = 1350 MHz, A_OUT = –2 dBFS	85
		f_IN = 1850 MHz, A_OUT = –2 dBFS	83
		f_IN = 2100 MHz, A_OUT = –2 dBFS	82
IL spur	Interleaving spur: f_S / 2 – f_IN,	f_IN = 100 MHz, A_OUT = –2 dBFS	91	dBc
		f_IN = 300 MHz, A_OUT = –2 dBFS	87
		f_IN = 950 MHz, A_OUT = –2 dBFS	83
		f_IN = 1200 MHz, A_OUT = –2 dBFS	82
		f_IN = 1350 MHz, A_OUT = –2 dBFS	82
		f_IN = 1850 MHz, A_OUT = –2 dBFS	82
		f_IN = 2100 MHz, A_OUT = –2 dBFS	80
HD2 IL	Interleaving spur for HD2: f_S / 2 – HD2	f_IN = 100 MHz, A_OUT = –2 dBFS	86	dBc
		f_IN = 300 MHz, A_OUT = –2 dBFS	87
		f_IN = 950 MHz, A_OUT = –2 dBFS	83
		f_IN = 1200 MHz, A_OUT = –2 dBFS	80
		f_IN = 1350 MHz, A_OUT = –2 dBFS	79
		f_IN = 1850 MHz, A_OUT = –2 dBFS	79
		f_IN = 2100 MHz, A_OUT = –2 dBFS	80
Worst spur	Spurious-free dynamic range (excluding HD2, HD3, HD4, HD5, and interleaving spurs IL and HD2 IL)	f_IN = 100 MHz, A_OUT = –2 dBFS	80	dBc
		f_IN = 300 MHz, A_OUT = –2 dBFS	82
		f_IN = 950 MHz, A_OUT = –2 dBFS	80
		f_IN = 1200 MHz, A_OUT = –2 dBFS	82
		f_IN = 1350 MHz, A_OUT = –2 dBFS	79
		f_IN = 1850 MHz, A_OUT = –2 dBFS	80
		f_IN = 2100 MHz, A_OUT = –2 dBFS	81
IMD3	Third-order intermodulation distortion	f_IN1 = 940 MHz, f_IN2 = 960 MHz, A_OUT = –8 dBFS (each tone)	75	dBFS

(1) The ADC internal resistance = 65 Ω, the driving source resistance = 50 Ω.

(2) Minimum values are specified at A_OUT = –3 dBFS.

7.7 Digital Requirements

PARAMETER		TEST CONDITIONS	MIN	NOM	MAX	UNIT
DIGITAL INPUTS (RESET, SCLK, SEN, SDIN, PDN, GPIO1, GPIO2, GPIO3, GPIO4)
V_IH	High-level input voltage		0.8			V
V_IL	Low-level input voltage				0.4	V
I_IH	High-level input current			50		µA
I_IL	Low-level input current			–50		µA
C_i	Input capacitance			4		pF
DIGITAL OUTPUTS (SDOUT, GPIO1, GPIO2, GPIO3, GPIO4)
V_OH	High-level output voltage		AVDD19–0.1	AVDD19		V
V_OL	Low-level output voltage				0.1	V
DIGITAL INPUTS (SYSREFP and SYSREFM; SYNCBP and SYNCBM; Requires External Biasing)
V_ID	Differential input voltage		350	450	800	mV_PP
V_CM	Input common-mode voltage		1.05	1.2	1.325	V
DIGITAL OUTPUTS (JESD204B Interface: DA[3:0], DB[3:0], Meets JESD204B LV-0IF-11G-SR Standard)
\|V_OD\|	Output differential voltage			700		mV_PP
\|V_OCM\|	Output common-mode voltage			450		mV
	Transmitter short-circuit current	Transmitter pins shorted to any voltage between –0.25 V and 1.45 V	–100		100	mA
z_os	Single-ended output impedance			50		Ω
C_o	Output capacitance	Output capacitance inside the device, from either output to ground		2		pF

7.8 Timing Requirements

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and ADC sampling rate = 2.6 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)

		MIN	NOM	MAX	UNIT
SAMPLE TIMING
	Aperture delay	250		750	ps
	Aperture delay matching between two channels on the same device		±15		ps
	Aperture delay matching between two devices at the same temperature and supply voltage		±150		ps
	Aperture jitter, clock amplitude = 2 V_PP		90		f_S
	Fast overrange latency, ADC sample to FOVR indication on GPIO pins		70		Input clock cycles
t_PD	Propagation delay time: logic gates and output buffer delay (does not change with f_S)		6		ns
SYSREF TIMING⁽¹⁾
t_{SU_SYSREF}	SYSREF setup time: referenced to clock rising edge, 1.5 GSPS	140	70		ps
t_{H_SYSREF}	SYSREF hold time: referenced to clock rising edge, 1.5 GSPS	50	20		ps
	Valid transition window sampling period: t_{SU_SYSREF} – t_{H_SYSREF}, 1.5 GSPS	476			ps
JESD OUTPUT INTERFACE TIMING
UI	Unit interval: 12.5 Gbps	80	100	400	ps
	Serial output data rate	2.5	10.0	12.5	Gbps
	Rise, fall times: 1-pF, single-ended load capacitance to ground		60		ps
	Total jitter: BER of 1E-15 and lane rate = 12.5 Gbps		25		%UI
	Random jitter: BER of 1E-15 and lane rate = 12.5 Gbps		0.99		%UI, rms
	Deterministic jitter: BER of 1E-15 and lane rate = 12.5 Gbps		9.1		%UI, pk-pk

(1) Common-mode voltage for the SYSREF input is kept at 1.2 V.

ADC32RF42 digital_inpt_outpts_sbas747.gif

V_OCM is not the same as V_ICM. Similarly, V_OD is not the same as V_ID.

Figure 1. Logic Levels for Digital Inputs and Outputs

Figure 2. SYSREF Timing Diagram

7.9 Typical Characteristics

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and ADC sampling rate = 1.5 GHz, 65536 points FFT, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)

SFDR = 73 dBc, SNR = 62.4 dBFS, SINAD = 62 dBFS,
THD = 71 dBc, HD2 = –75 dBFS, HD3 = –78 dBFS,
SFDR (non HD2, HD3) = 85 dBc, IL spur = 81 dBFS

Figure 3. FFT for 100-MHz Input Signal

SFDR = 65 dBc, SNR = 62.3 dBFS, SINAD = 61 dBFS,
THD = 64 dBc, HD2 = –67 dBFS, HD3 = –75 dBFS,
SFDR (non HD2, HD3) = 74 dBc, IL spur = 82 dBFS

Figure 5. FFT for 300-MHz Input Signal

SFDR = 72 dBc, SNR = 60.2 dBFS, SINAD = 60 dBFS, THD = 71 dBc, HD2 = –74 dBFS, HD3 = –87 dBFS, SFDR (non HD2, HD3) = 80 dBFS, IL spur = 80 dBFS

Figure 7. FFT for 1200-MHz Input Signal

SFDR = 59 dBc, SNR = 57.9 dBFS, SINAD = 56 dBFS,
HD2 = –61 dBFS, HD3 = –69 dBFS,
SFDR (non HD2, HD3) = 81 dBc, THD = 58 dBc,
IL spur = 83 dBFS

Figure 9. FFT for 2100-MHz Input Signal

f_IN1 = 940 MHz, f_IN2 = 960 MHz,
A_OUT = –36 dBFS, IMD = 94 dBFS

Figure 11. FFT for Two-Tone Input Signal (–36 dBFS)

Figure 13. Spurious-Free Dynamic Range vs Input Frequency

Figure 15. Signal-to-Noise Ratio vs Input Frequency

f_IN = 950 MHz, A_IN = –2 dBFS

Figure 17. Spurious-Free Dynamic Range vs AVDD Supply and Temperature

f_IN = 950 MHz, A_IN = –2 dBFS

Figure 19. Spurious-Free Dynamic Range vs DVDD Supply and Temperature

f_IN = 950 MHz, A_IN = –2 dBFS

Figure 21. Spurious-Free Dynamic Range vs AVDD19 Supply and Temperature

f_IN = 950 MHz, A_IN = –2 dBFS

Figure 23. Performance vs Clock Amplitude

f_IN = 1850 MHz, A_IN = –2 dBFS, SNR = 63.8 dBFS,
SFDR (includes IL) = 78 dBc, f_S = 1500 MSPS

Figure 25. FFT in 4x Decimation

f_IN = 1850 MHz, A_IN = –2 dBFS, SNR = 66 dBFS,
SFDR (includes IL) = 77 dBc, f_S = 1500 MSPS

Figure 27. FFT in 8x Decimation

f_IN = 1850 MHz, A_IN = –2 dBFS, SNR = 65.9 dBFS,
SFDR (includes IL) = 74 dBc, f_S = 1500 MSPS

Figure 29. FFT in 10x Decimation

f_IN = 1850 MHz, A_IN = –2 dBFS, SNR = 68.1 dBFS,
SFDR (includes IL) = 80.9 dBc, f_S = 1500 MSPS

Figure 31. FFT in 16x Decimation

SFDR = 65 dBc, SNR = 62.3 dBFS, SINAD = 61 dBFS,
THD = 64 dBc, HD2 = –67 dBFS, HD3 = –73 dBFS,
SFDR (non HD2, HD3) = 89 dBc, IL spur = 81 dBFS

Figure 4. FFT for 185-MHz Input Signal

SFDR = 70 dBc, SNR = 60.8 dBFS, SINAD = 60 dBFS,
THD = 69 dBc, HD2 = –72 dBFS, HD3 = –78 dBFS,
SFDR (non HD2, HD3) = 81 dBc, IL spur = 82 dBFS

Figure 6. FFT for 950-MHz Input Signal

SFDR = 70 dBc, SNR = 58.7 dBFS, SINAD = 58 dBFS,
HD2 = –72 dBFS, HD3 = –75 dBFS,
SFDR (non HD2, HD3) = 79 dBc, THD = 68 dBc,
IL spur = 80 dBFS

Figure 8. FFT for 1850-MHz Input Signal

f_IN1 = 940 MHz, f_IN2 = 960 MHz, A_OUT = –8 dBFS, IMD = 75 dBFS

Figure 10. FFT for Two-Tone Input Signal (–8 dBFS)

Figure 12. Intermodulation Distortion vs Input Amplitude (940 MHz and 960 MHz)

Figure 14. IL Spur vs Input Frequency

f_IN = 950 MHz, A_IN = –2 dBFS

Figure 16. Signal-to-Noise Ratio vs AVDD Supply and Temperature

f_IN = 950 MHz, A_IN = –2 dBFS

Figure 18. Signal-to-Noise Ratio vs DVDD Supply and Temperature

f_IN = 950 MHz, A_IN = –2 dBFS

Figure 20. Signal-to-Noise Ratio vs AVDD19 Supply and Temperature

f_IN = 950 MHz, A_IN = –2 dBFS

Figure 22. Performance vs Amplitude

f_IN = 950 MHz, A_IN = –2 dBFS

Figure 24. Performance vs Clock Duty Cycle

f_IN = 1850 MHz, A_IN = –2 dBFS, SNR = 65 dBFS,
SFDR (includes IL) = 75 dBc, f_S = 1500 MSPS

Figure 26. FFT in 6x Decimation

f_IN = 1850 MHz, A_IN = –2 dBFS, SNR = 65.8 dBFS,
SFDR (includes IL) = 74 dBc, f_S = 1500 MSPS

Figure 28. FFT in 9x Decimation

f_IN = 1850 MHz, A_IN = –2 dBFS, SNR = 66.4 dBFS,
SFDR (includes IL) = 74.1 dBc, f_S = 1500 MSPS

Figure 30. FFT in 12x Decimation