LMX2571 低功耗、高性能 PLLatinum RF 合成器，采用 FSK 调制
- ZHCSDH8 March 2015 LMX2571
  
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LMX2571 低功耗、高性能 PLLatinum RF 合成器，采用 FSK 调制

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1 特性

输出频率范围：10MHz 至 1344MHz
低相位噪声和毛刺
- 12.5kHz 偏移 @ 480MHz 时为 –123dBc/Hz
- 1MHz 偏移 @ 480MHz 时为 –145dBc/Hz
- 标准化锁相环 (PLL) 噪底为 –231dBc/Hz
- 杂散优于 –75dBc/Hz
新型 FastLock 技术，缩短了锁定时间
新型整数边界毛刺去除技术
集成 5V 电荷泵和输出驱动器，用于外部压控振荡器 (VCO) 操作
2、4 和 8 电平或者任意电平数直接数字移频键控 (FSK) 调制
一个 TX/RX 输出或两个扇出输出
晶振、XO 或差分参考时钟输入
低电流消耗
- 39mA 典型合成器模式（内部 VCO）
- 9mA 典型 PLL 模式（外部 VCO）
24 位分数 N Δ-Σ 调制器

2 应用

双工模式数字专业双向无线电
- dPMR、DMR、PDT、P25 Phase I
低功耗无线电通信系统
- 卫星通信调制解调器
- 无线麦克风
- 专有无线连接
手持式测试和测量设备

3 说明

LMX2571 是一款低功耗、高性能、宽带 PLLatinum™ 射频 (RF) 合成器，该合成器集成了 Δ-Σ 分数 N PLL、多核压控振荡器 (VCO)、可编程输出分压器以及两个输出缓冲器。 VCO 内核的工作频率高达 5.376GHz，持续输出频率范围为 10MHz 至 1344MHz。

该合成器还可搭配外部 VCO 使用。在此配置下，需使用专用的 5V 电荷泵和输出分压器。

该合成器还包含一个独特的可编程乘法器，有助于去除毛刺，即使毛刺落在整数边界，系统也仍能够使用任一通道。

其输出具有 SPDT 开关，可用作 FDD 无线电应用中的发送/接收开关。并且可同时导通两个开关，以便同时提供双输出。

LMX2571 通过编程或相应引脚来支持直接数字 FSK 调制。该器件支持离散电平 FSK、脉冲成形 FSK 以及模拟 FM 调制。

该器件采用了一项全新的 FastLock 技术，即使在外部 VCO 与窄带回路滤波器搭配使用时，用户也能够在不到 1.5ms 的时间内从一个频率切换至另一频率。

器件信息⁽¹⁾

器件型号	封装	封装尺寸（标称值）
LMX2571	WQFN (36)	6.00mm x 6.00mm

如需了解所有可用封装，请见数据表末尾的可订购产品附录。

4 修订历史记录

日期	修订版本	注释
2015 年 3 月	*	最初发布。

5 Pin Configuration and Functions

WQFN (NJK) Package

36 Pins

Top View

Pin Functions

PIN		TYPE	DESCRIPTION
NAME	NO.	TYPE	DESCRIPTION
Bypass1	2	Bypass	Place a 100-nF capacitor to GND.
Bypass2	3	Bypass	Place a 100-nF capacitor to GND.
CE	19	Input	Chip Enable input. Active HIGH powers on the device.
CLK	11	Input	MICROWIRE clock input.
CPout	25	Output	Internal VCO charge pump access point to connect to a 2^nd order loop filter.
CPoutExt	30	Output	5-V charge pump output used in PLL mode (external VCO).
DAP	0	GND	The DAP should be grounded.
DATA	12	Input	MICROWIRE serial data input.
Fin	24	Input	High frequency AC coupled input pin for an external VCO. Leave it open or AC coupled to GND if not being used.
FSK_D0	7	Input	FSK data bit 0 (FSK PIN mode) / I2S FS input (FSK I2S mode).
FSK_D1	6	Input	FSK data bit 1 (FSK PIN mode) / I2S DATA input (FSK I2S mode).
FSK_D2	5	Input	FSK data bit 2 (FSK PIN mode).
FSK_DV	4	Input	FSK data valid input (FSK PIN mode) / I2S CLK input (FSK I2S mode).
FLout1	29	Output	FastLock output control 1 for external switch. Output is HIGH when F1 is selected.
FLout2	28	Output	FastLock output control 2 for external switch. Output is HIGH when F2 is selected.
GND	23	GND	VCO ground.
GND	31	GND	Charge pump ground.
GND	35	GND	OSCin ground.
LE	13	Input	MICROWIRE latch enable input.
MUXout	10	Output	Multiplexed output that can be assigned to lock detect or readback serial data output.
NC	8,14, 26	NC	Do not connect these pins.
OSCin	34	Input	Reference clock input.
OSCin*	36	Input	Complementary reference clock input.
RFoutRx	16	Output	RF output used to drive receive mixer. Selectable open drain or push-pull output.
RFoutTx	17	Output	RF output used to drive transmit signal. Selectable open drain or push-pull output.
TrCtl	18	Input	Transmit/Receive control. This pin controls the RF output port and the output frequency selection.
Vcc3p3	1, 9, 20, 27	Supply	Connect to 3.3-V supply.
VccIO	15, 33	Supply	Supply for digital logic interface. Connect to 3.3-V supply.
VcpExt	32	Supply	Supply for 5-V charge pump. Connect to 5-V supply in PLL mode. Connect to either 3.3-V or 5-V supply in synthesizer mode.
VrefVCO	22	Bypass	LDO output. Place a 100-nF capacitor to GND.
VregVCO	21	Bypass	Bias circuitry for the VCO. Place a 2.2-µF capacitor to GND.

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
V_CC	Power supply voltage	–0.3	3.6	V
V_IO	IO supply voltage	–0.3	3.6	V
V_IN	IO input voltage		V_CC + 0.3	V
V_CP	Charge pump supply voltage		5.25	V
T_J	Junction temperature		150	°C
T_STG	Storage temperature	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±1500	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

			MIN	MAX	UNIT
V_CC	Power supply voltage		3.15	3.45	V
V_IO	IO supply voltage			V_CC	V
V_CP	Charge pump supply voltage	PLL mode (external VCO)		5	V
V_CP	Charge pump supply voltage	Synthesizer mode (internal VCO)	V_CC	5	V
T_A	Ambient temperature		–40	85	°C
T_J	Junction Temperature			125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		LMX2571	UNIT
		WQFN (NJK)
		36 PINS
R_θJA	Junction-to-ambient thermal resistance	32.9	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	14.5
R_θJB	Junction-to-board thermal resistance	6.3
ψ_JT	Junction-to-top characterization parameter	0.2
ψ_JB	Junction-to-board characterization parameter	6.3
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	2.0

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

3.15 V ≤ V_CC ≤ 3.45 V, V_IO = V_CC, –40 °C ≤ T_A ≤ 85 °C, except as specified. Typical values are at V_CC = V_IO = 3.3 V, V_CP = 3.3 V or 5 V in synthesizer mode, V_CP = 5 V in PLL mode, T_A = 25 °C.

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
CURRENT CONSUMPTION
I_CC	Total current in synthesizer mode (internal VCO)	f_OUT = 480 MHz SE OSCin	Configuration A⁽¹⁾		39		mA
			Configuration B⁽²⁾		44
			Configuration C⁽³⁾		46
			Configuration D⁽⁴⁾		51
I_PLL	Total current in PLL mode (external VCO)		Configuration E⁽⁵⁾		9
			Configuration F⁽⁶⁾		15
			Configuration G⁽⁷⁾		21
I_CCPD	Power down current	CE = 0V or POWERDOWN bit = 1 V_CC = 3.3 V, Push-pull output			0.9
OSCIN REFERENCE INPUT
f_OSCin	OSCin frequency range	Single-ended or differential input		10		150	MHz
V_OSCin	OSCin input voltage⁽⁸⁾	Single-ended input		1.4		3.3	V
V_OSCin	OSCin input voltage⁽⁸⁾	Differential input		0.15		1.5	V
CRYSTAL REFERENCE INPUT
f_XTAL	Crystal frequency range	Fundamental model, ESR < 200 Ω		10		40	MHz
C_IN	OSCin input capacitance				1		pF
MULT
f_MULTin	MULT input frequency	MULT > Pre-divider Not supported with crystal reference input		10		30	MHz
f_MULTout	MULT output frequency			60		130	MHz
PLL
f_PD	Phase detector frequency					130	MHz
K_PD	Charge pump current⁽⁹⁾	Programmable minimum value	Internal charge pump		312.5		µA
		Programmable minimum value	5-V charge pump		625
		Per programmable step	Internal charge pump		312.5
		Per programmable step	5-V charge pump		625
		Programmable maximum value	Internal charge pump		7187.5
		Programmable maximum value	5-V charge pump		6875
PN_{PLL_1/f}	Normalized PLL 1/f noise⁽¹⁰⁾	At maximum charge pump current	Internal charge pump		–124		dBc/Hz
PN_{PLL_1/f}	Normalized PLL 1/f noise⁽¹⁰⁾		5-V charge pump		–120		dBc/Hz
PN_{PLL_Flat}	Normalized PLL noise floor⁽¹⁰⁾		Internal charge pump		–231		dBc/Hz
PN_{PLL_Flat}	Normalized PLL noise floor⁽¹⁰⁾		5-V charge pump		–226		dBc/Hz
f_RFin	External VCO input frequency			100		1400	MHz
P_RFin	External VCO input power	f_RFin < 1 GHz		–10			dBm
P_RFin	External VCO input power	f_RFin ≥ 1 GHz		–5			dBm
VCO
f_VCO	VCO frequency			4300		5376	MHz
K_VCO	VCO gain⁽¹¹⁾	f_VCO = 4800 MHz			56		MHz/V
\| ΔT_CL \|	Allowable temperature drift⁽¹²⁾	VCO not being re-calibrated, –40 °C ≤ T_A ≤ 85 °C				125	°C
t_VCOCal	VCO calibration time	f_OSCin = f_PD = 100 MHz			140		µs
PN_VCO	Open loop VCO phase noise	f_OUT = 480 MHz	100 Hz offset		–32.4		dBc/Hz
			1 kHz offset		–62.3
			10 kHz offset		–92.1
			100 kHz offset		–121.1
			1 MHz offset		–144.5
			10 MHz offset		–156.8
RF OUTPUT
f_OUT	RF output frequency	Synthesizer mode		10		1344	MHz
f_OUT	RF output frequency	PLL mode, RF output from buffer		10		1400	MHz
P_TX, P_RX	RF output power	f_OUT = 480 MHz	Power control bit = 6		0		dBm
H2_RFout	Second harmonic	f_OUT = 480 MHz	Power control bit = 6		–25		dBc
DIGITAL FSK MODULATION
FSK_Level	FSK level⁽¹³⁾	FSK PIN mode		2		8
FSK_Baud	FSK baud rate⁽¹⁴⁾	Loop bandwidth = 200 kHz			100		kSPs
FSK_Dev	FSK deviation	Configuration H⁽¹⁵⁾			±39		kHz
DIGITAL INTERFACE
V_IH	High level input voltage			1.4		V_IO	V
V_IL	Low level input voltage					0.4	V
I_IH	High level input current	V_IH = 1.75 V		–25		25	µA
I_IL	Low level input current	V_IL= 0 V		–25		25	µA
V_OH	High level output voltage	I_OH = 500 µA		2			V
V_OL	Low level output voltage	I_OL = –500 µA			0	0.4	V

(1) f_OSCin = 19.44 MHz, MULT = 1, Prescaler = 4, f_PD = 19.44 MHz, one RF output, output type = push pull, output power = –3 dBm

(2) f_OSCin = 19.44 MHz, MULT = 1, Prescaler = 2, f_PD = 19.44 MHz, one RF output, output type = push pull, output power = –3 dBm

(3) f_OSCin = 19.44 MHz, MULT = 5, Prescaler = 2, f_PD = 19.44 MHz, one RF output, output type = push pull, output power = –3 dBm

(4) f_OSCin = 19.44 MHz, MULT = 5, Prescaler = 2, f_PD = 97.2 MHz, one RF output, output type = push pull, output power = –3 dBm

(5) f_OSCin = 19.44 MHz, MULT = 1, f_PD = 19.44 MHz, output from VCO

(6) f_OSCin = 19.44 MHz, MULT = 1, f_PD = 19.44 MHz, one RF output, output type = push pull, output power = –3 dBm

(7) f_OSCin = 19.44 MHz, MULT = 1, f_PD = 19.44 MHz, two RF outputs, output type = push pull, output power = –3 dBm

(8) See OSCin Configuration for definition of OSCin input voltage.

(9) This is referring to the total base charge pump current. In PLL mode, this is equal to EXTVCO_CP_IDN + EXTVCO_CP_IUP. In synthesizer mode, this is equal to CP_IDN + CP_IUP. See Table 5, Table 6 and Table 7 for details.

(10) Measured with a clean OSCin signal with a high slew rate using a wide loop bandwidth. The noise metrics model the PLL noise for an infinite loop bandwidth as:
PLL_Total = 10 * log[10^{(PLL_Flat / 10)} + 10^{(PLL_Flicker / 10)}]
PLL_Flat = PN1Hz + 20 * log(N) + 10 * log(f_PD)
PLL_Flicker = PN10kHz – 10 * log(Offset / 10 kHz) + 20 * log(f_OUT / 1 GHz)

(11) The VCO gain changes as a function of the VCO core and frequency. See Integrated VCO for details.

(12) Not tested in production. Ensured by characterization. Allowable temperature drift refers to programming the device at an initial temperature and allowing this temperature to drift WITHOUT reprogramming the device, and still have the device stay in lock. This change could be up or down in temperature and the specification does not apply to temperatures that go outside the recommended operating temperatures of the device.

(13) The data showed here simply specifies the range of discrete FSK level that is supported in PIN mode. PIN mode supports 2-, 4- and 8-level of FSK modulation. If arbitrary level of FSK modulation is desired, use FSK SPI™ FAST mode or FSK I2S mode. See Direct Digital FSK Modulation for details.

(14) The baud rate is limited by the loop bandwidth of the PLL loop. As a general rule of thumb, it is desirable to have the loop bandwidth at least twice the baud rate.

(15) f_PD = 100 MHz, DEN = 2²⁴, CHDIV1 = 5, CHDIV2 = 2, Prescaler = 2, FSK step value = 32716, 32819. The maximum achievable frequency deviation depends on the configuration, see Direct Digital FSK Modulation for details.

6.6 Timing Requirements

3.15 V ≤ V_CC ≤ 3.45 V, V_IO = V_CC, –40 °C ≤ T_A ≤ 85 °C, except as specified. Typical values are at V_CC = V_IO = 3.3 V, T_A = 25 °C.

			MIN	UNIT
MICROWIRE TIMING
t_ES	Clock to enable low time	See Figure 1	5	ns
t_CS	Data to clock setup time		2	ns
t_CH	Data to clock hold time		2	ns
t_CWH	Clock pulse width high		5	ns
t_CWL	Clock pulse width low		5	ns
t_CES	Enable to clock setup time		5	ns
t_EWH	Enable pulse width high		2	ns

Figure 1. MICROWIRE Timing Diagram

There are several other considerations for programming:

A slew rate of at least 30 V/µs is recommended for the CLK, DATA and LE. The same apply for other digital control signals such as FSK_D[0:2] and FSK_DV signals.
The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the LE signal, the data is sent from the shift register to an active register.
The LE pin may be held high after programming, causing the LMX2571 to ignore clock pulses.
When CLK or DATA lines are shared between devices, it is recommended to divide down the voltage to the CLK, DATA, and LE pins closer to the minimum voltage. This provides better noise immunity.
If the CLK and DATA lines are toggled while the VCO is in lock, as is sometimes the case when these lines are shared with other parts, the phase noise may be degraded during the time of this programming.