LMX2581 具有集成 VCO 的宽带频率合成器

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1 特性

输出频率：50MHz 至 3760MHz
输入时钟频率高达 900MHz
相位检测器速率高达 200MHz
支持分数和整数两种模式
标准化锁相环 (PLL) 相位噪声为 –229dBc/Hz
标准化 PLL 1/f 噪声为 –120.8dBc/Hz
对于 2.5GHz 载波，1MHz 偏移时的压控振荡器 (VCO) 相位噪声为 –137dBc/Hz
整数模式下的抖动为 100fs（均方根 (RMS)）
可编程的分数调制器阶数
可编程的分数分母
最高达 +12dBm 的可编程输出功率
可编程的 32 级电荷泵电流
提供相应的可编程选项以使用外部 VCO
数字锁定检测
3 线串行接口和读回功能
单电源电压范围：3.15V 至 3.45V
支持最低至 1.6V 的逻辑电平

2 应用

无线基础设施（通用移动通信系统 (UMTS)、长期演进技术 (LTE)、全球微波互联接入 (WiMax)、多标准基站）
无线宽带
测试和测量
时钟发生

3 说明

LMX2581 是一款低噪声宽带频率合成器，其集成有 Δ-Σ 分数 N PLL、多核 VCO、可编程输出分频器以及两个差动输出缓冲器。 VCO 的频率范围为 1880MHz 至 3760MHz，既可以直接发送至输出缓冲器，也可以进行 2 至 38 范围内的分频。每个缓冲器在 2700MHz 频率下都能够提供 -3dBm 至 +12dBm 范围内的输出功率。该器件集成有低噪声 LDO，用于实现出色的抗扰度和稳定性能。.

该合成器是一款高度可编程的器件，用户可通过编程来优化其性能。在分数模式下，分母和调制器阶数均可编程，并且还可以配置抖动。用户还能够直接指定 VCO 内核或者完全旁路掉内部 VCO。最后，该器件还包含许多便捷功能，例如断电、快速锁定、自动静音以及锁定检测。所有寄存器均可通过简单的 3 线接口进行编程，并且还提供读回功能。

LMX2581 通过 3.3V 单电源供电运行，并且采用 32 引脚 5.0mm × 5.0mm 超薄型四方扁平无引线 (WQFN) 封装。

器件信息⁽¹⁾

器件型号	封装	封装尺寸（标称值）
LMX2581	WQFN (32)	5.00mm x 5.00mm

如需了解所有可用封装，请见数据表末尾的可订购产品附录。

4 简化电路原理图

5 修订历史记录

Changes from F Revision (March 2014) to G Revision

Added "over operating free-air temperature range (unless otherwise noted)" in Absolute Maximum Ratings and Recommended Operating Conditions.Go
Added footnotes to HBM, CDM, and MM in Handling Ratings table.Go
Moved explanations of Typical Characteristics plots from plot footnotes to Feature Description section.Go
Moved Impact of Temperature on VCO Phase Noise into Feature Description section.Go
Added some description of modulator noise floor and Table 4. Go
Changed -89 to -83 in Table 11Go
Moved "Triggering Registers" to "Register Maps" section.Go
Changed order of subsections in Application and Implementation section.Go
Changed -- inverted color scheme of Figure 23, Figure 24, and Figure 25 to enhance readabilityGo
Added “器件和文档支持”的链接。已通篇添加应用笔记 AN-1879 (SNAA062) 的链接。Go

Changes from E Revision (Novmeber 2013) to F Revision

Added 数据表结构和组织结构。已添加、更新或重命名以下部分：器件信息表；应用和实施；电源相关建议；布局；器件和文档支持；机械、封装和订购信息Go
Changed Clarified that typical PLL noise metrics are measured at max charge pump gain. Go
Added Typical Characteristics curves. Go
Changed Recommendation for OSC_FREQ bit for input frequencies > 64 MHz Go
Added Application and Implementation section with schematic.Go
Added Power Supply RecommendationsGo
Added Layout Go

Changes from D Revision (April 2013) to E Revision

Changed -- Output Power upgraded from 5 dBm to 7.3 dBm for OUTx_PWR = 15. Go
Added output power spec for OUT_PWR = 45. Go
Changed Fvco = 1.9 GHz: 10 kHz: –84.8 to –85.4; 100 kHz: –113.7 to –114.5; 1 MHz: –136.7 to –137.Go
Changed Fvco = 2.2 GHz: 40 MHz: –155.2 to –156.1. Go
Changed Fvco = 2.7 GHz: 100 kHz: –111.1 to –112.2; 1 MHz: –135.5 to –136.0; 10 MHz: –152.9 to –153.1; 40 MHz: –154.6 to –155. Go
Changed Fvco = 3.3 GHz: 10 kHz: –77.9 to –79; 100kHz: –108 to –108.6; 1 MHz: –132.4 to –132.6; 10 MHz: –151.5 to –152; 40 MHz: –153.6 to –155. Go
Added updates on using 0–Delay ModeGo
Added more information on how to use readback. Go
Changed SPURS: Fpd spur for Fpd = 100 MHz upgraded from –71 to –81 dBc. Improvement due to better board layout.Go
Changed -- Fixed PLL_R[7:0] box drawn incorrectly in the register map.Go
Added updates to the applications section on impact of OUTx_PWR.
Updates to the application section regarding dithering were added.Go

Changes from C Revision (April 2013) to D Revision

Added Typical spur specifications to Electrical Characteristics.Go
Changed -- Updates to the programming section were made regarding programming recommendations, clarifications to the register map, and more details for the programming word descriptions. Go
Added More information to the applications section regarding fractional spurs Go

Changes from B Revision (October 2013) to C Revision

Changed 国家数据表风格至 TI 格式。Go

Changes from A Revision (August 2012) to B Revision

Added information about resistor and inductor pull-up. Go

6 Pin Configuration and Functions

32-Pin

DAP Package

(Top View)

Pin Functions

PIN		TYPE	DESCRIPTION
NUMBER	NAME	TYPE	DESCRIPTION
0	DAP	GND	The DAP should be grounded.
1	CLK	Input	MICROWIRE Clock Input. High Impedance CMOS input.
2	DATA	Input	MICROWIRE Data. High Impedance CMOS input.
3	LE	Input	MICROWIRE Latch Enable. High Impedance CMOS input.
4	CE	Input	Chip Enable Pin.
5	FLout	Output	Fastlock Output. This can switch in an external resistor to the loop filter during locking to improve lock time.
6	VccCP	Supply	Charge Pump Supply.
7	CPout	Output	Charge Pump Output.
8	GND	GND	Ground for the Charge Pump.
9	GND	GND	Ground for the N and R divider.
10	VccPLL	Supply	Supply for the PLL.
11	Fin	Input	High frequency input pin for an external VCO. Leave Open or Ground if not used.
12	RFoutA+	Output	Differential divided output. For single-ended operation, terminate the complimentary side with a load equivalent to the load at this Pin.
13	RFoutA-	Output	Differential divided output. For single-ended operation, terminate the complimentary side with a load equivalent to the load at this pin.
14	RFoutB+	Output	Differential divided output. For single-ended operation, terminate the complimentary side with a load equivalent to the load at this pin.
15	RFoutB-	Output	Differential divided output. For single-ended operation, terminate the complimentary side with a load equivalent to the load at this pin.
16	VccBUF	Supply	Supply for the Output Buffer.
17	VccVCO	Supply	Supply for the VCO.
18	GND	GND	Ground Pin for the VCO. This can be attached to the regular ground. Ensure a solid trace connects this pin to the bypass capacitors on pins 19, 23, and 24.
19	VbiasVCO	Output	Bias circuitry for the VCO. Place a 2.2 µF capacitor to GND (Preferably close to Pin 18).
20	Vtune	Input	VCO tuning voltage input. See the functional description regarding the minimum capacitance to put at this pin.
21	GND	GND	VCO ground.
22	VrefVCO	Output	VCO capacitance. Place a capacitor to GND (Preferably close to Pin 18). This value should be between 5% and 10% of the capacitance at pin 24. Recommended value is 1 µF.
23	VbiasCOMP	Output	VCO bias voltage temperature compensation circuit. Place a minimum 10 µF capacitor to GND (Preferably close to Pin 18). If it is possible, use more capacitance to slightly improve VCO phase noise.
24	VregVCO	Output	VCO regulator output. Place a minimum 10 µF capacitor to GND (Preferably close to Pin 18). If it is possible, use more capacitance to slightly improve VCO phase noise.
25	LD	Output	Multiplexed output that can perform lock detect, PLL N and R counter outputs, Readback, and other diagnostic functions.
26	BUFEN	Input	Enable pin for the RF output buffer. If not used, this can be overwritten in software.
27	GND	GND	Digital Ground.
28	VccDIG	Supply	Digital Supply.
29	OSCin	Input	Reference input clock.
30	MUXout	Output	Multiplexed output that can perform lock detect, PLL N and R counter outputs, Readback, and other diagnostic functions..
31	GND	GND	Ground for the fractional circuitry.
32	VccFRAC	Vcc	Supply for the fractional circuitry.