bq24190、bq24192 和 bq24192I 是高度集成的开关模式电池管理和系统电源路径管理器件,适用于各类、平板电脑和其他便携式设备的单节锂离子和锂聚合物电池。
产品型号 | 封装 | 封装尺寸(标称值) |
---|---|---|
bq24190 | VQFN (24) | 4.00mm x 4.00mm |
bq24192 | ||
bq24192I |
Changes from A Revision (October 2012) to B Revision
它的低阻抗电源路径对开关模式运行效率进行了优化、减少了电池充电时间并延长了放电阶段的电池寿命。具有充电和系统设置的 I2C 串行接口使得此器件成为一个真正地灵活解决方案。
此器件支持宽范围的输入源,其中包括标准 USB 主机端口,USB 充电端口和高功率 DC 适配器。为了设定默认输入电流限值,bq24190 根据 USB 电池充电规范 1.2 检测输入源,而 bq24192 和 bq24192I 从系统检测电路(如 USB PHY 器件)中获取结果。bq24190、192 和 192I 符合 USB 2.0 和 USB 3.0 电源规范,具有输入电流和电压调节功能。同时,bq24190、bq24192 和 bq24192I 具有高达 1.3A 的限流能力,能够为 VBUS 提供 5V 电压,符合 USB On-the-Go (OTG) 运行功率额定值规范。
电源路径管理将系统电压调节为稍稍高于电池电压,但是又不会下降到低于 3.5V 最小系统电压(可编程)。借助于这个特性,即使在电池电量完全耗尽或者电池被拆除时,系统也能保持运行。当达到输入电流限值或电压限值时,电源路径管理自动将充电电流减少为 0。随着系统负载持续增加,电源路径在满足系统电源需求之前将电池放电。这个补充模式运行防止输入源过载。
此器件在无需软件控制情况下启动并完成一个充电周期。它自动检测电池电压并通过三个阶段为电池充电:预充电、恒定电流和恒定电压。在充电周期的末尾,当充电电流低于在恒定电压阶段中预设定的限值时,充电器自动终止。当整个电池下降到低于再充电阈值时,充电器将自动启动另外一个充电周期。
bq24190、bq24192 和 bq24192I 提供针对电池充电和系统运行的多种安全 特性, 其中包括两组负温度系数热敏电阻监视、充电安全定时器和过压/过流保护。当结温超过 120°C(可设定)时,热调节减少充电电流。
STAT 输出报告充电状态和任何故障条件。bq24192 和 bq24192I 中的 PG 输出指示电源是否正常。 当故障发生时,INT 会立即通知主机。
bq24190、bq24192 和 bq24192I 采用 24 引脚、4.00mm x 4.00mm2 超薄型四方扁平无引线 (VQFN) 封装。
bq24190 | bq24192 | bq24192I | |
---|---|---|---|
I2C Address | 6BH | 6BH | 6BH |
USB Detection | D+/D– | PSEL | PSEL |
Default VINDPM | 4.36 V | 4.36 V | 4.44 V |
Default Battery Voltage | 4.208 V | 4.208 V | 4.112 V |
Default Charge Current | 2.048 A | 2.048 A | 1.024 A |
Default Adapter Current Limit | 1.5 A | 3 A | 1.5 A |
Maximum Pre-Charge Current | 2.048 A | 2.048 A | 640 mA |
Charging Temperature Profile | Cold/Hot 2 TS pins |
Cold/Hot 2 TS pins |
Cold/Hot 2 TS pins |
Status Output | STAT | STAT, PG | STAT, PG |
STAT During Fault | Blinking at 1 Hz | Blinking at1 Hz | 10 k to ground |
PIN | NUMBER | TYPE | DESCRIPTION | |
---|---|---|---|---|
bq24190 | bq24192 bq24192I |
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VBUS | VBUS | 1,24 | P | Charger Input Voltage. The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID with VBUS on source. Place a 1-µF ceramic capacitor from VBUS to PGND and place it as close as possible to IC. (Refer to Application Information Section for details) |
D+ | – | 2 | I Analog |
Positive line of the USB data line pair. D+/D– based USB host/charging port detection. The detection includes data contact detection (DCD) and primary detection in bc1.2. |
– | PSEL | 2 | I Digital |
Power source selection input. High indicates a USB host source and Low indicates an adapter source. |
D– | – | 3 | I Analog |
Negative line of the USB data line pair. D+/D– based USB host/charging port detection. The detection includes data contact detection (DCD) and primary detection in bc1.2. |
– | PG | 3 | O Digital |
Open drain active low power good indicator. Connect to the pull up rail via 10-kΩ resistor. LOW indicates a good input source if the input voltage is between UVLO and ACOV, above SLEEP mode threshold, and current limit is above 30 mA. |
STAT | STAT | 4 | O Digital |
Open drain charge status output to indicate various charger operation. Connect to the pull up rail via 10-kΩ. LOW indicates charge in progress. HIGH indicates charge complete or charge disabled. When any fault condition occurs, STAT pin in bq24190, bq24192 blinks at 1 Hz, and STAT pin in bq24192I has a 10-kΩ resistor to ground. |
SCL | SCL | 5 | I Digital |
I2C Interface clock. Connect SCL to the logic rail through a 10-kΩ resistor. |
SDA | SDA | 6 | I/O Digital |
I2C Interface data. Connect SDA to the logic rail through a 10-kΩ resistor. |
INT | INT | 7 | O Digital |
Open-drain Interrupt Output. Connect the INT to a logic rail via 10-kΩ resistor. The INT pin sends active low, 256-us pulse to host to report charger device status and fault. |
OTG | OTG | 8 | I Digital |
USB current limit selection pin during buck mode, and active high enable pin during boost mode. |
In buck mode with USB host (PSEL=High), when OTG = High, IIN limit = 500 mA and when OTG = Low, IIN limit = 100 mA. | ||||
The boost mode is activated when the REG01[5:4] = 10 and OTG pin is High. | ||||
CE | CE | 9 | I Digital |
Active low Charge Enable pin. Battery charging is enabled when REG01[5:4] = 01 and CE pin = Low. CE pin must be pulled high or low. |
ILIM | ILIM | 10 | I Analog |
ILIM pin sets the maximum input current limit by regulating the ILIM voltage at 1 V. A resistor is connected from ILIM pin to ground to set the maximum limit as IINMAX = (1V/RILIM) × 530. The actual input current limit is the lower one set by ILIM and by I2C REG00[2:0]. The minimum input current programmed on ILIM pin is 500 mA. |
TS1 | TS1 | 11 | I Analog |
Temperature qualification voltage input #1. Connect a negative temperature coefficient thermistor. Program temperature window with a resistor divider from REGN to TS1 to GND. Charge suspends when either TS pin is out of range. Recommend 103AT-2 thermistor. |
TS2 | TS2 | 12 | I Analog |
Temperature qualification voltage input #2. Connect a negative temperature coefficient thermistor. Program temperature window with a resistor divider from REGN to TS2 to GND. Charge suspends when either TS pin is out of range. Recommend 103AT-2 thermistor. |
BAT | BAT | 13,14 | P | Battery connection point to the positive terminal of the battery pack. The internal BATFET is connected between BAT and SYS. Connect a 10 µF closely to the BAT pin. |
SYS | SYS | 15,16 | P | System connection point. The internal BATFET is connected between BAT and SYS. When the battery falls below the minimum system voltage, switch-mode converter keeps SYS above the minimum system voltage. (Refer to Application Information Section for inductor and capacitor selection.) |
PGND | PGND | 17,18 | P | Power ground connection for high-current power converter node. Internally, PGND is connected to the source of the n-channel LSFET. On PCB layout, connect directly to ground connection of input and output capacitors of the charger. A single point connection is recommended between power PGND and the analog GND near the IC PGND pin. |
SW | SW | 19,20 | O Analog |
Switching node connecting to output inductor. Internally SW is connected to the source of the n-channel HSFET and the drain of the n-channel LSFET. Connect the 0.047-µF bootstrap capacitor from SW to BTST. |
BTST | BTST | 21 | P | PWM high side driver positive supply. Internally, the BTST is connected to the anode of the boost-strap diode. Connect the 0.047-µF bootstrap capacitor from SW to BTST. |
REGN | REGN | 22 | P | PWM low side driver positive supply output. Internally, REGN is connected to the cathode of the boost-strap diode. Connect a 4.7-µF (10-V rating) ceramic capacitor from REGN to analog GND. The capacitor should be placed close to the IC. REGN also serves as bias rail of TS1 and TS2 pins. |
PMID | PMID | 23 | O Analog |
Connected to the drain of the reverse blocking MOSFET and the drain of HSFET. Given the total input capacitance, connect a 1-µF capacitor on VBUS to PGND, and the rest all on PMID to PGND. (Refer to Application Information Section for details) |
Thermal Pad | – | – | P | Exposed pad beneath the IC for heat dissipation. Always solder thermal pad to the board, and have vias on the thermal pad plane star-connecting to PGND and ground plane for high-current power converter. |