AWRL1432 Device Silicon Errata
Silicon Revisions ES1.1,
ES2.0
1 Introduction
2 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of Radar / mmWave sensor devices. Each of the Radar devices has one of the two prefixes: XAx or AWRLx (for example: XA1432BGABL). These prefixes represent evolutionary stages of product development from engineering prototypes (XI) through fully qualified production devices AWRLx.
Device development evolutionary flow:
| XA — | Experimental device that is not necessarily representative of the final device's electrical specifications and may not use production assembly flow. |
| AWRL — | Production version of the silicon die that is fully qualified. |
XAx devices are shipped with the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Texas Instruments recommends that these devices not to be used in any production system as their expected end –use failure rate is still undefined.
3 Device Markings
Figure 3-1 shows an example of the AWRL1432 Radar Device's package symbolization.
Figure 3-1 Example of Device Part
MarkingsThis identifying number contains the following information:
- Line 1: TI Logo
- Line 1: Device Number
- Line 2: Safety Level and
Security Grade
- Q = Non-Functional Safety
- B = ASIL B capable
- G = General
- A = Authenticated Boot
- Line 3: Lot Trace Code
- YM = Year/Month Code
- Z = Assembly Site Code
- LLL = Assembly Lot
- 9= Primary Site Code
- Line 4:
- 843/791 = Device Identifier
- B/A = Die Revision
- AMF = Package Identifier
- G1 = "Green" Package Build (must be underlined)
4 Advisory to Silicon Variant / Revision Map
| Advisory Number | Advisory Title | AWRL1432 | AWRL1432 |
|---|---|---|---|
| ES1.1 | ES2.0 | ||
| Analog / Millimeter Wave | |||
| ANA #51 |
Continuous Wave Streaming CZ mode: Sudden jump in RX output codes every 20.97152 msec |
x | x |
| ANA #52 | Slicer LDO Test LOAD (TLOAD) not disabled after startup | x | |
| Digital Subsystem | |||
| DIG #1 | ePWM: Glitch during Chopper mode of operation | x | x |
| DIG #2 | UART: UARTA cannot be used to wake up the sequencer from Deep Sleep Low Power Mode | x | |
| DIG #3 | UART: Limited UART baud rates | x | x |
| DIG #4 | RS232: AutoBaud Rate feature doesn't support trimmed RCOSC variation | x | x |
| DIG #5 | Internal Bus access to SPI for data transfer not supported when SPI smart-idle mode is enabled | x | x |
| DIG #6 | CRC: CRC 8-bit data width and CRC8-SAE-J1850 and CRC8-H2F possible use in CAN module is not supported | x | x |
| DIG #7 | APPSS Cortex-M4 doesn't get the correct error response when cluster 3 retention memories are accessed in low-power deep-sleep powered down state | x | |
| DIG #8 | Shared RAM clock gating default values | x | x |
| DIG #9 | TOP_IO_MUX register space not accessible from RS232 for debug purposes | x | x |
| DIG #10 | Incorrect behavior of frame stop API | x | x |
| DIG #14 | Corrupted Data Store for Partial Write in Shared Memory | x | x |
| DIG #15 | Boot failure, if metaimage is multiple of 2K | x | |
| DIG #16 | Boot failure for images less than size 8k over SPI | x | x |