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  • J7200 DRA821 Processor Silicon Revision 1.0, 2.0

    • SPRZ491E December   2020  – December 2024 DRA821U , DRA821U-Q1

       

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  • J7200 DRA821 Processor Silicon Revision 1.0, 2.0
  1.   1
  2. 1Modules Affected
  3. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  4. 3Silicon Revision 1.0, 2.0 Usage Notes and Advisories
    1. 3.1 Silicon Revision 1.0, 2.0 Usage Notes
    2. 3.2 Silicon Revision 1.0, 2.0 Advisories
    3.     i2049
    4.     i2062
    5.     i2091
    6.     i2103
    7.     i2116
    8.     i2123
    9. 3.3 i2126
    10. 3.4 i2127
    11.     i2134
    12.     i2137
    13.     i2146
    14. 3.5 i2151
    15.     i2157
    16.     i2159
    17.     i2160
    18.     i2161
    19.     i2163
    20.     i2166
    21.     i2177
    22.     i2182
    23.     i2183
    24.     i2184
    25.     i2185
    26.     i2186
    27.     i2187
    28.     i2189
    29.     i2196
    30.     i2197
    31.     i2201
    32.     i2205
    33.     i2207
    34.     i2208
    35.     i2209
    36.     i2216
    37.     i2217
    38.     i2221
    39.     i2222
    40.     i2227
    41.     i2228
    42.     i2232
    43.     i2233
    44.     i2234
    45.     i2235
    46.     i2237
    47.     i2241
    48.     i2242
    49.     i2243
    50.     i2244
    51.     i2245
    52.     i2246
    53.     i2249
    54.     i2253
    55.     i2257
    56.     i2274
    57.     i2275
    58.     i2277
    59.     i2278
    60.     i2279
    61.     i2283
    62.     i2306
    63.     i2307
    64.     i2310
    65.     i2311
    66.     i2312
    67.     i2320
    68.     i2326
    69.     i2329
    70.     i2351
    71.     i2360
    72.     i2361
    73.     i2362
    74.     i2366
    75.     i2371
    76.     i2372
    77.     i2383
    78.     i2401
    79.     i2409
    80.     i2413
    81.     i2414
    82.     i2418
    83.     i2419
    84.     i2422
    85.     i2424
    86.     i2435
    87.     i2459
  5.   Trademarks
  6.   Revision History
  7. IMPORTANT NOTICE
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Errata

J7200 DRA821 Processor Silicon Revision 1.0, 2.0

1 Modules Affected

Table 1-1 shows the module(s) that are affected by each usage note.

Table 1-1 Usage Note by Modules
MODULE USAGE NOTE
N/A

Table 1-2 shows the module(s) that are affected by each advisory.

Table 1-2 Advisories by Modules
MODULE ADVISORY SILICON REVISIONS AFFECTED
SR 1.0 SR 2.0
ADC i2151 — ADC: Debounce time control register YES YES
Boot i2307 — Boot: ROM does not properly select OSPI clocking modes based on BOOTMODE YES YES
i2360 — Boot: Ethernet RMII Boot Mode is not supported YES YES
i2361 — Boot: SPI and xSPI BOOTMODE Pin Mapping changes for SR2.0 NO YES
i2366 — Boot: ROM does not comprehend specific JEDEC SFDP features for 8D-8D-8D operation YES YES
i2371 — Boot: ROM code may hang in UART boot mode during data transfer YES YES
i2372 — Boot: ROM doesn't support select multi-plane addressing schemes in Serial NAND boot NO YES
i2459 — Boot: PCIe Boot Mode is not supported YES YES
i2413 — Boot: HS-FS ROM boots corrupted ROM boot image YES YES
i2414 — Boot: Ethernet PHY Scan and Bring-Up Flow doesn't work with PHYs that don't support Auto Negotiation YES YES
i2418 — Boot: Secure ROM Panic due to Certificate Info not present YES YES
i2419 — Boot: When disabling deskew calibration, ROM does not check if deskew calibration was enabled YES YES
i2422 — Boot: ROM timeout for MMCSD filesystem boot too long YES YES
i2435 — Boot: ROM timeout for eMMC boot too long YES YES
CBASS i2207 — CBASS: Command Arbitration Blocking YES YES
i2235 — CBASS Null Error Interrupt Not Masked By Enable Register YES YES
CC i2221 — CC: Invasive and Non-Invasive debug enable settings are reset by MCU_RESETz YES YES
i2222 — Compute Cluster: A72 Corepac unable to be powered down YES YES
CP i2283 — Restrictions on how CP Tracer Debug Probes can be used YES YES
CPSW i2184 — CPSW: IET express traffic policing issue YES YES
i2185 — CPSW: Policer color marking issue YES YES
i2208 — CPSW: ALE IET Express Packet Drops YES YES
i2401 — CPSW: Host Timestamps Cause CPSW Port to Lock up YES YES
DCC i2209 — DCC: Incorrect clock selection YES NO
DDR i2157 — DDR: Controller anomaly in setting wakeup time for low power states YES YES
i2159 — DDR: VRCG high current mode must be used during LPDDR4 CBT YES YES
i2160 — DDR: Valid VRef Range Must be Defined During LPDDR4 Command Bus Training YES YES
i2166 — DDR: Entry and exit to/from Deep Sleep low-power state can cause PHY internal clock misalignment YES YES
i2182 — DDR: Dual-rank non-power-of-2 density not supported with row-cs-bank-col address mapping YES YES
i2186 — DDR rate limited to 2666 MT/s 1333 MHz clock YES NO
i2232 — DDR: Controller postpones more than allowed refreshes after frequency change YES YES
i2244 — DDR: Valid stop value must be defined for write DQ VREF training YES YES
i2274 — DDR: Including DDR in BSCAN causes current alarm on the DDR supply YES NO
DMADVR i2233 — DMADVR: Link/link_safer sync issue between MAIN and MCU YES YES
DMSC i2245 — DMSC: Firewall Region requires specific configuration YES YES
i2275 — DMSC Secure Boot ROM: Potential Secure Boot vulnerability with explicit EC curve parameters in X.509 certificate YES NO
ECC AGGR i2049 — ECC AGGR: Potential IP Clockstop/reset sequence hang due to pending ECC Aggregator interrupts YES YES
I3C i2197 — I3C: Slave mode is not supported YES YES
i2205 — I3C Command fetched during pending IBI is not properly processed in some cases YES YES
i2216 — I3C: Command execution may fail during slave-initiated IBI address byte reception YES YES
IA i2196 — IA: Potential deadlock scenarios in IA YES YES
JTAG i2228 — JTAG: TAP used by Debuggers may be inaccessible if TRSTn device pin is never asserted YES NO
MCAN i2278 — MCAN: Message Transmit order not guaranteed from dedicated Tx Buffers configured with same Message ID YES YES
i2279 — MCAN: Specification Update for dedicated Tx Buffers and Tx Queues configured with same Message ID YES YES
MCU i2217 — Recommended POST selection via MCU_BOOTMODE[09:08] YES NO
MDIO i2329 — MDIO: MDIO interface corruption (CPSW and PRU-ICSS) YES YES
MMCSD i2312 — MMCSD: HS200 and SDR104 Command Timeout Window Too Small YES YES
MSMC i2116 — MSMC: Set-hazarding logic withholding RT access waiting on NRT access completion YES YES
i2187 — MSMC: Cache Resize to 0 Refreshes Tags instead of Updating them YES YES
i2201 — MSMC: Incorrect Parity Detect on bytecount YES NO
OSPI i2189 — OSPI: Controller PHY Tuning Algorithm YES YES
i2249 — OSPI: Internal PHY Loopback and Internal Pad Loopback clocking modes with DDR timing inoperable YES YES
i2351 — OSPI: Controller does not support Continuous Read mode with NAND Flash YES YES
i2383 — OSPI: 2-byte address is not supported in PHY DDR mode YES YES
PCIe i2183 — PCIe: Link up failure when unused lanes are not assigned to PCIe Controller YES YES
i2237 — PCIe: SerDes Reference Clock Output does not comply to Vcross, Rise-Fall Matching, and Edge Rate limits YES NO
i2241 — PCIe: The SerDes PCIe Reference Clock Output can exceed the 5.0 GT/s Data Rate RMS jitter limit YES NO
i2242 — PCIe: The 4-L SerDes PCIe Reference Clock Output is temporarily disabled while changing Data Rates YES YES
i2243 — PCIe: Timing requirement for disabling output refclk during L1.2 substate is not met YES YES
i2246 — PCIe: Automatic compliance entry fails when unused SERDES lanes are not assigned to PCIe Controller YES YES
i2326 — PCIe: MAIN_PLLx operating in fractional mode, which is required for enabling SSC, is not compliant with PCIe Refclk jitter limits YES YES
PLL i2424 — PLL: PLL Programming Sequence May Introduce PLL Instability YES YES
POK i2277 — POK: De-Glitch (filter) is based upon only two samples YES NO
PRG i2253 — PRG: CTRL_MMR STAT registers are unreliable indicators of POK threshold failure YES YES
PSIL i2137 — Clock stop operation can result in undefined behavior YES YES
R5FSS i2161 — R5FSS: Debugger cannot access VIM module while it is active YES NO
i2227 — R5FSS: Error interrupt CCM_COMPARE_STAT_PULSE_INTR incorrectly driven YES YES
RAT i2062 — RAT: Error Interrupt Triggered Even When Error Logging Disable Is Set YES YES
RINGACC i2177 — RINGACC: The ring accelerator’s debug transaction trace stream can be corrupted by certain ring access sequences YES YES
ROM Code i2306 — ROM Code: Need to turn off internal termination resistors in SERDES YES NO
Safety i2103 — Safety Modules: Incorrect Reporting of ECC_GRP, ECC_BIT and ECC_TYPE Information for Functional Safety Errors YES YES
SGMII i2362 — 10-100M SGMII: Marvell PHY does not ignore the preamble byte resulting in link failure YES YES
STOG i2123 — STOG: Timed Out Emulation Debug write responses from the Slave Gasket always return Success YES YES
i2126 — STOG: Error miscounting when there are two concurrent timeouts or two concurrent unexpected responses YES YES
i2127 — STOG: SRC side write data bus hang when a write command timeout occurs the same cycle as last acceptance on DST side YES YES
UDMA i2146 — UDMA: Force teardown bitfield readback is masked in realtime TX/RX registers YES YES
i2320 — UDMA, UDMAP: Descriptors and TRs required to be returned unfragmented YES YES
UDMAP i2163 — UDMAP: UDMA transfers with ICNTs and/or src/dst addr NOT aligned to 64B fail when used in "event trigger" mode YES YES
i2234 — UDMA: TR15 hangs if ICNT0 is less than 64 bytes YES YES
USART i2310 — USART: Erroneous clear/trigger of timeout interrupt YES YES
i2311 — USART: Spurious DMA Interrupts YES YES
USB i2091 — 2.0 PHY hangs if received signal amplitude crosses squelch threshold multiple times within the same packet YES YES
i2134 — USB: 2.0 compliance receive sensitivity test limitation YES YES
i2409 — USB2 PHY locks up due to short suspend YES YES
xSPI i2257 — xSPI boot mode redundant image boot failure YES NO

2 Nomenclature, Package Symbolization, and Revision Identification

 

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