SNVU596A October   2018  – July 2025 LP87521-Q1 , LP87522-Q1 , LP87523-Q1 , LP87524-Q1 , LP87525-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Setup
    1. 2.1 SCL/SDA Pins
    2. 2.2 NRST Pin
    3. 2.3 ENx (GPIOx) Pins
    4. 2.4 nINT
  6. 3Configuration
    1. 3.1 Configuration Sequence
    2. 3.2 Default OTP Configurations
    3. 3.3 Recommended Order of Configuring Registers Through I2C
      1. 3.3.1 Voltage Settings
      2. 3.3.2 Other Regulator Settings
      3. 3.3.3 GPO Settings
      4. 3.3.4 Clock Sync Functions
      5. 3.3.5 PGOOD Settings
      6. 3.3.6 Interrupt Settings
      7. 3.3.7 Startup and Shutdown Sequence
      8. 3.3.8 Set ENx Pin Control Bits
      9. 3.3.9 Set EN_BUCKx Bits
  7. 4Revision History
User's Guide

LP8752x-Q1 Configuration Guide