ITU-T G.8262 Compliance Test Results for the LMK5C33216
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1 Introduction
The LMK5C33216 device is a high-performance network clock generator, synchronizer, and jitter attenuator with advanced reference clock selection and hitless switching capabilities designed to meet the stringent requirements of communications infrastructure applications.
This document contains the summary of the test setups and measured results highlighting compliance to ITU-T G.8262 (Timing characteristics of a synchronous Ethernet equipment slave clock) standard. The device-under-test (LMK5C33216) was configured using Texas Instruments' TICS Pro Silicon EVM Programming Tool. Unless specified otherwise, the LMK5C33216 Digital PLL loop bandwidth for EEC-Option 1 was set to 10 Hz and for EEC-Option 2 to 0.1 Hz.
All measurement results included in this document are for DPLL1. The measurement results for DPLL1 are an accurate representation of compliance characteristics for all three DPLLs. All three DPLLs passed standard compliance test requirements.
Throughout this document, the acronym MTIE stands for maximum time interval error and the acronym TDEV stands for time deviation.
Testing was performed using the Calnex Rb/GPS frequency reference and Calnex Paragon-T hardware. Other test hardware was used as required for the measurements.
Notable features of this high-performance device includes:
- Hitless Switching with minimal phase transients (< 100 ps)
- Ultra High-Performance VCO allows use of a low-cost holdover reference without sacrificing performance
- High-Performance DPLL Channel with Programmable loop bandwidth for jitter and wander filtering suitable for EEC Option 1 and EEC Option 2
- Reference Priority Selection, Gapped Clock and Runt Pulse Detectors, Automatic/Manual Switchover, Holdover, and Tuning Word History
| SECTION | DESCRIPTION | EEC OPT 1 (SECTION IN G.8262) | EEC OPT 2 (SECTION IN G.8262) | COMPLIANT |
|---|---|---|---|---|
| WANDER GENERATION | ||||
| Section 2.1 | MTIE EEC Option 1; Must not exceed MTIE mask | 8.1.1 | Yes | |
| Section 2.2 | TDEV EEC Option 1; Must not exceed TDEV mask | 8.1.1 | Yes | |
| Section 2.3 | MTIE EEC Option 2; Must not exceed MTIE mask | 8.1.2 | Yes | |
| Section 2.3 | TDEV EEC Option 2; Must not exceed TDEV mask | 8.1.2 | Yes | |
| WANDER TRANSFER | ||||
| Section 3.1 | Transfer function of the PLL for EEC Option 1 and EEC Option 2; Must meet bandwidth requirements | 10.1 | 10.2 | Yes |
| Section 3.2 | Wander Transfer TDEV G.8262 for EEC Option 2; Must not exceed TDEV mask | 10.2 | Yes | |
| WANDER TOLERANCE | ||||
| Section 4.1 | Wander Tolerance EEC Option 1; Must tolerate at least input wander defined by MTIE/TDEV mask | 9.1.1 | Yes | |
| Section 4.2 | Wander Tolerance EEC Option 2; Must tolerate at least input wander defined by TDEV mask | 9.1.2 | Yes | |
| JITTER TOLERANCE | ||||
| Section 5.1 | Jitter Tolerance for EEC Option 1 and EEC Option 2; Must tolerate jitter defined by UI mask | 9.2.1 | 9.2.1 | Yes |
| PHASE TRANSIENT GENERATION | ||||
| Section 6.1 | Short Term Phase Transient EEC Option 1; Must not exceed limits set by standard | 11.1.1 | Yes | |
| Section 6.2 | Short Term Phase Transient EEC Option 2; Must not exceed MTIE mask set by standard | 11.1.2 11.4.2 | Yes | |
| Section 6.3 | Phase Transient Generation with Signal Interruptions EEC Option 1; Must not exceed phase variation limit | 11.3.1 | Yes | |
| Section 6.4 | Phase Discontinuity EEC Option 1; Must not exceed phase variation limits | 11.4.1 | Yes | |
| Section 6.5 | Phase Discontinuity EEC Option 2; Must not exceed MTIE mask set by standard | 11.4.2 | Yes | |
| HOLDOVER PERFORMANCE | ||||
| Section 7.1 | Holdover EEC Option 1; Must not exceed TIE mask set by standard | 11.2.1 | Yes | |
| Section 7.2 | Holdover EEC Option 2; Must meet TIE mask set by standard | 11.2.2 | Yes | |
| FREE-RUN ACCURACY | ||||
| Section 8.1 | Free-run Accuracy EEC Option 1 and Option 2; Must not exceed ±4.6 ppm | 6.1 | 6.2 | Yes |
| PULL-IN AND HOLD-IN | ||||
| Section 9 | Pull-in and Hold-in EEC Option 1 and Option 2; Minimum pull-in range and hold-in range must be ±4.6 ppm | 7.1.1 | 7.1.2 7.2.2 | Yes |
2 Wander Generation
The following MTIE and TDEV ECC option 1 and 2 tests measure the amount of wander generated by the LMK5C33216. Figure 2-1 shows the setup used for these tests.
Figure 2-1 Test Setup for Wander Generation. 2.1 Wander Generation MTIE Option 1, G.8262 EEC Option 1
While the DPLL is locked to an input clock that is wander-free, it will not generate wander that exceeds the green MTIE masks shown in Figure 2-2 and Figure 2-3. These masks can be seen in Figure 1 in the G.8262 specification. There is no noise modulation applied to the input for this test. The LMK5C33216 passed the Wander Generation MTIE Option 1, G.8262 EEC Option 1 requirement as shown in Figure 2-2 and Figure 2-3.
Figure 2-2 Wander Generation MTIE Option 1, G.8262 EEC
Option 1 Results, Tested at Constant Room
Temperature With DPLL Bandwidth of 10 Hz
Figure 2-3 Wander Generation MTIE Option 1, G.8262 EEC
Option 1 Results, Tested at Temperature of 85°C
With DPLL Bandwidth of 10 Hz