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  • TPD1S414 USB Charger Overvoltage, Surge, and ESD Protection for VBUS Pin

    • SLLSEH9B October   2013  – July 2016

      PRODUCTION DATA.  

  • CONTENTS
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  • TPD1S414 USB Charger Overvoltage, Surge, and ESD Protection for VBUS Pin
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics (EN, ACK Pins)
    6. 6.6  Electrical Characteristics (OVP Circuit)
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics (nFET)
    9. 6.9  Supply Current Consumption
    10. 6.10 Thermal Shutdown Feature
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Overvoltage Protection on VBUS_CON up to 30-V DC
      2. 7.3.2 Low RON nFET Switch Supports Host and Charging Mode
      3. 7.3.3 ±15-kV IEC 61000-4-2 Level 4 ESD Protection
      4. 7.3.4 100-V IEC 61000-4-5 µs Surge Protection
      5. 7.3.5 Start-Up and OVP Recovery Delay
      6. 7.3.6 Integrated Input Enable and Status Output Signal
      7. 7.3.7 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 VBUS_CON < VUVLO
      2. 7.4.2 VUVLO < VBUS_CON < VOVP
      3. 7.4.3 VBUS_CON > VOVP
      4. 7.4.4 OVP Operation
      5. 7.4.5 Host/OTG Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 USB VBUS Voltage Range
        2. 8.2.2.2 USB VBUS Operating Current
        3. 8.2.2.3 VBUS_CON and VBUS_SYS Capacitance
        4. 8.2.2.4 IEC 61000-4-5 100-V Open-Circuit Surge
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resource
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE
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DATA SHEET

TPD1S414 USB Charger Overvoltage, Surge, and ESD Protection for VBUS Pin

1 Features

  • Overvoltage Protection at VBUS_CON Up to 30-V DC
  • Low RON nFET Switch Supports Host and Charging Mode
  • Internal 15-ms Start-Up Delay
  • Internal 30-ms Soft-Start Delay to Minimize the USB Inrush Current
  • Transient Protection for VBUS Line:
    • IEC 61000-4-2 Contact Discharge ±15 kV
    • IEC 61000-4-2 Air Gap Discharge ±15 kV
    • IEC 61000-4-5 Open-Circuit Voltage 100 V
  • Integrated Input Enable and Status Output Signal
  • Thermal Shutdown (TSD) Feature
  • Space-Saving DSBGA Package: (1.4 mm × 1.89 mm)

2 Applications

  • End Equipment
    • Mobile Phones
    • Tablets
    • Wearables
    • Electronic-Point-of-Sale (EPOS)
  • Interfaces
    • USB 2.0
    • USB 3.0
    • USB Type C

3 Description

The TPD1S414 device is a single-chip solution for a USB connector’s VBUS line protection. The bidirectional nFET switch ensures safe current flow in both charging and host mode while protecting the internal system circuits from any overvoltage conditions at the VBUS_CON pin. On the VBUS_CON pin, this device can handle overvoltage protection up to 30 V. After the EN pin toggles low, the TPD1S414 waits 20 ms before turning ON the nFET through a soft-start delay. ACK pin indicates the FET is completely turned ON.

The typical application interface for the TPD1S414 is the VBUS line in USB connectors. Typical end equipment for TPD1S414 are mobiles phones, tablets, wearables, and electronic-point-of-sale (EPOS). The TPD1S414 can also be applied to any system using an interface with a 5-V power rail.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TPD1S414 DSBGA (12) 1.40 mm × 1.89 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application Schematic

TPD1S414 TPD1S414_App_Diagram_2.gif

4 Revision History

Changes from A Revision (October 2013) to B Revision

  • Added ESD Ratings table, Detailed Description section, Application and Implementation section, Power Supply Recommendations section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo

Changes from * Revision (October 2013) to A Revision

  • Changed text in the DESCRIPTION From: TPD1S414 waits 15 ms before turning ON the nFET To: TPD1S414 waits 20 ms before turning ON the nFETGo
  • Deleted Continuous forward current through the FET body diode, IDIODE from the ABSOLUTE MAXIMUM RATINGS tableGo
  • Deleted Peak input current on VBUS_CON pin, IBUS from the ABSOLUTE MAXIMUM RATINGS tableGo
  • Added Voltage on ACK pin to the ABSOLUTE MAXIMUM RATINGS tableGo
  • Added Continuous current on VBUS_CON and VBUS_SYS pins to the RECOMMENDED OPERATING CONDITIONS tableGo
  • Added Continuous forward current through the FET body diode, IDIODE to the RECOMMENDED OPERATING CONDITIONS tableGo
  • Added values to the THERMAL INFORMATION tableGo
  • Changed the IHOST_LEAK MAX value From: 160 To: 200 µA in the SUPPLY CURRENT CONSUMPTION tableGo
  • Deleted graphs: Enabling the Load Switch, Connecting VBUS_CON, and OVP Operation from the TIMING DIAGRAMS sectionGo
  • Changed horizontal axis labeling on Figure 7Go
  • Changed Figure 10Go
  • Added text to the APPLICATION INFORMATION sectionGo

5 Pin Configuration and Functions

YZ Package
12-Pin DSBGA
Top View - See Through
TPD1S414 po_sllseh9.gif

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
ACK B1 O Open-Drain Acknowledge pin. See Table 2.
EN C1 I Enable Active-Low Input. Drive EN low to enable the switch. Drive EN high to disable the switch.
VBUS_CON B3, C2, C3 I/O Connect to USB connector VBUS pin;
IEC61000-4-2 ESD protection
IEC61000-4-5 Surge protection
VBUS_SYS A2, A3, B2 I/O Connect to internal VBUS plane
GND A1, A4, B4, C4 Ground Connect to PCB ground plane

Table 1. 12-YZ Pin Mapping

1 2 3 4
A GND VBUS_SYS VBUS_SYS GND
B ACK VBUS_SYS VBUS_CON GND
C EN VBUS_CON VBUS_CON GND

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
Supply voltage from USB connector, VBUS_CON –0.3 30 V
Internal supply DC voltage rail on the PCB, VBUS_SYS –0.5 7 V
Voltage on EN pin –0.5 7 V
Voltage on ACK pin –0.5 7 V
Output load capacitance, CLOAD VBUS_SYS pin 0.1 50 µF
Input capacitance, CON VBUS_CON pin 0.1 50 µF
Operating free-air temperature, TA –40 85 °C
Storage temperature, Tstg –40 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
IEC 61000-4-2 contact discharge ±15000 V
IEC 61000-4-2 air-gap discharge ±15000 V
IEC 61000-4-5 Peak Pulse Current (tp = 8/20 µs) VBUS_CON pin 21 A
IEC 61000-4-5 Peak Pulse Power (tp = 8/20 µs) VBUS_CON pin 700 W
IEC 61000-4-5 Open circuit voltage (tp = 1.2/50 µs) VBUS_CON pin 100 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±2000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN NOM MAX UNIT
VBUS_CON Supply voltage from USB connector 5.9 V
VBUS_SYS Internal supply DC voltage rail on the PCB 5.9 V
CLOAD Output load capacitance VBUS_SYS pin 2.2 µF
CIN Input capacitance VBUS_CON pin 1 µF
RPULLUP Pullup resistor ACK pin 4.3 100 kΩ
IVBUS Continuous current on VBUS_CON and VBUS_SYS pins VBUS_CON
VBUS_SYS 		3.5 A
IDIODE Continuous current through the FET body diode 1 A

6.4 Thermal Information

THERMAL METRIC(1) TPD1S414 UNIT
YZ (DSBGA)
12 PINS
RθJA Junction-to-ambient thermal resistance 89 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 0.6 °C/W
RθJB Junction-to-board thermal resistance 16.3 °C/W
ψJT Junction-to-top characterization parameter 2.7 °C/W
ψJB Junction-to-board characterization parameter 16.2 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance n/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics (EN, ACK Pins)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input voltage, EN 1.2 6 V
VIL Low-level input voltage, EN 0.8 V
IIL Input leakage current EN VI = 3.3 V 1 µA
VOL Low-level output voltage, ACK IOL = 3 mA 0.4 V

6.6 Electrical Characteristics (OVP Circuit)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOVP_RISING Input overvoltage protection threshold, VBUS_CON VBUS_CON increasing from 5 V 6 6.2 6.4 V
VHYS_OVP Hysteresis on OVP, VBUS_CON VBUS_CON decreasing from 7 V to 5 V 50 mV
VOVP_FALLING Input overvoltage protection threshold, VBUS_CON VBUS_CON decreasing from 7 V to 5 V 5.93 6.37 V
VUVLO Input undervoltage lockout, VBUS_CON VBUS_CON voltage rising from 0 V to 5 V 3.1 3.3 3.5 V
VHYS_UVLO Hysteresis on UVLO, VBUS_CON Difference between rising and falling UVLO thresholds 100 mV
VUVLO_FALLING Input undervoltage lockout, VBUS_CON VBUS_CON voltage rising from 5 V to 0 V 3 3.2 3.4 V
VUVLO_SYS VBUS_SYS undervoltage lockout, VBUS_SYS VBUS_SYS voltage rising from 0 V to 5 V 3.1 3.6 4.3 V
VHYS_UVLO_SYS VBUS_SYS UVLO Hysteresis, VBUS_SYS Difference between rising and falling UVLO thresholds on VBUS_SYS 480 mV
VUVLO_SYS_FALL VBUS_SYS undervoltage lockout, VBUS_SYS VBUS_SYS voltage falling from 7 V to 5 V 3 3.2 3.4 V

6.7 Timing Requirements

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
tDELAY USB charging turnon delay Measured from EN asserted LOW to nFET beginning to Turn ON(1) excluding soft-start time 20 ms
tSS USB charging rise time (soft-start delay) Measure from VBUS_SYS rises above 25% (with 1-MΩ load/ NO CLOAD) until ACK goes Low (10%) 25 ms
tOFF_DELAY USB charging turnoff time Measured from EN asserted High to VBUS_SYS falling to 10% with RLOAD = 10 Ω and No CLOAD on VBUS_SYS 4 µs
OVERVOLTAGE PROTECTION
tOVP_response OVP response time Measured from OVP Condition to FET Turn OFF(2). VBUS_CON rises at 1V / 100 ns 100 ns
tOVP_Recov Recovery time Measured from OVP Clear to FET Turn ON(3) 20 ms
(1) Shown in Figure 1.
(2) Parameters provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's product warranty.
(3) Excludes soft-start time

6.8 Switching Characteristics (nFET)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RDS(on) Switch ON-resistance VBUS_CON = 5 V, IOUT = 1 A,
TA = 25˚C		 39 50 mΩ

6.9 Supply Current Consumption

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IVBUS_SLEEP VBUS_CON operating current consumption Measured at VBUS_CON pin,
VBUS_CON = 5 V, EN =5V 		30 70 µA
IVBUS Measured at VBUS_CON pin,
VBUS_CON = 5 V, EN 0 V and no load		 175 373 µA
IVBUS_SYS VBUS_CON operating current consumption Measured at VBUS_SYS pin,
VBUS_SYS = 5 V, EN = 0 V and
VBUS_CON = Hi Z		 175 373 µA
IHOST_LEAK Host mode leakage current Measured at VBUS_SYS,
VBUS_CON = Hi Z, EN = 5 V,
VBUS_SYS = 5 V		 90 200 µA

6.10 Thermal Shutdown Feature

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TSHDN Thermal shutdown Junction temperature 145 °C
Thermal-shutdown hysteresis Junction temperature 35 °C
TPD1S414 thermal_shutdown_sllseh9.gif Figure 1. Thermal Shutdown Operation

6.11 Typical Characteristics

TPD1S414 C001_SLLSEH9.png Figure 2. Input Supply Current vs Supply Voltage
TPD1S414 C003_SLLSEH9.png Figure 4. Normalized RDS(ON) vs Output Current
TPD1S414 C005_SLLSEH9.png Figure 6. Normalized TDELAY
TPD1S414 C007_SLLSEH9.png Figure 8. Power Up With 2.2 µF on VBUS_SYS
TPD1S414 C002_SLLSEH9.png Figure 3. Normalized RDS(ON) vs Temperature
TPD1S414 C004_SLLSEH9.png Figure 5. Normalized VOVP
TPD1S414 C006_SLLSEH9.png Figure 7. VOVP Response Time
TPD1S414 C008_SLLSEH9.png Figure 9. Response to a 100-V Surge

 
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