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  • SN54SC4T125-SEP Total Ionizing Dose (TID) Report

    • SCLK039 November   2023 SN54SC4T125-SEP

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  • SN54SC4T125-SEP Total Ionizing Dose (TID) Report
  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Device Information
    1. 1.1 Device Details
  5. 2Total Dose Test Setup
    1. 2.1 Test Overview
    2. 2.2 Test Description and Facilities
    3. 2.3 Test Setup Details
      1. 2.3.1 Bias Diagram
    4. 2.4 Test Configuration and Condition
  6. 3TID Characterization Test Results
    1. 3.1 TID Characterization Summary Results
    2. 3.2 Specification Compliance Matrix
  7. 4Reference Documents
  8. 5Appendix: HDR TID Report Data
  9. IMPORTANT NOTICE
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Radiation Report

SN54SC4T125-SEP Total Ionizing Dose (TID) Report

Abstract

This report covers the radiation characterization results of the SN54SC4T125-SEP radiation tolerant, single power supply quadruple buffer translator gate. The study was done to determine Total Ionizing Dose (TID) effects under high dose rate (HDR) up to 50 krad(Si) as a one time characterization. The results show that all samples passed within the specified limits up to 50 krad(Si). Radiation Lot Acceptance Testing (RLAT) will be performed using five units at a dose level of 30 krad(Si) for future wafer lots per MIL-STD-883 TM 1019.

The SN54SC4T125-SEP is packaged in a space enhanced plastic for low outgassing characteristics and is Single Event Latch-Up (SEL) immune up to 43 MeV-cm2 / mg, which makes the device an option for low Earth orbit space applications.

The SN54SC4T125-SEP Total Ionizing Dose (TID) Report covers the TID performance of all seven devices listed below. The SN54SC4T125-SEP device covers all functional blocks and active die area of the other six devices, which is why the device was selected for total ionizing dose testing for this group of logic gate devices.

  1. SN54SC4T125-SEP
  2. SN54SC3T97-SEP
  3. SN54SC3T98-SEP
  4. SN54SC4T00-SEP
  5. SN54SC4T02-SEP
  6. SN54SC4T32-SEP
  7. SN54SC4T86-SEP

Trademarks

All trademarks are the property of their respective owners.

1 Device Information

The SN54SC4T125-SEP contains four independent buffers with 3-state outputs and extended voltage operation to allow for level translation. Each buffer performs the Boolean function Y = A in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.2-V, 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels. The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (For example, 1.2-V input to 1.8-V output or 1.8-V input to 3.3-V output.) Additionally, the 5-V tolerant input pins enable down translation (For example, 3.3-V to 2.5-V output). The SN54SC4T125-SEP is a pure CMOS device and as a result, was tested at a High Dose Rate (HDR) for TID testing.

 

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