Paralleling LDO’s using ballast resistors have been discussed in the industry for many years. Previously, the analysis techniques that had been developed were limited to two parallel LDO’s and did not take into consideration nonideal parasitic effects such as PCB impedance. Design and analysis of ballast resistance has not previously been fully explored, forcing the practicing engineer to use look up tables or common values such as 20 mΩ seen in many reference designs. Unfortunately, these look up tables give no methods to calculate how these ballast resistance values impact the load voltage and could be overdesigned leading to degraded performance.

Modern systems require parallel LDO designs to meet more than just additional load current or spread the heat generated by the power dissipation of the LDOs. Methods to accurately design with more than two parallel LDO’s needed to be developed as many engineers want to use 5-10 parallel LDO’s to meet their load current requirements. The voltage at the load must be calculated to ensure it meets the system requirement. This technical white paper provides a new mathematical foundation to calculate the load current and load voltage for any number of parallel LDOs. From this, we can support a new generation of designs which may parallel any number of LDO’s to meet the system load voltage and load current while optimizing the ballast resistance to include the parasitic PCB impedance for maximum performance.

In a typical LDO, the voltage feedback amplifier (error amplifier) compares the sensed output voltage to the reference voltage and adjusts the feedback loop accordingly (Figure 2-1). The nonideal components of the error amplifier include the offset voltage (V_OS) and bias currents (I_BIAS). In an ideal LDO, there are no sources of error and the output voltage is configured using V_REF, R₁ and R₂.

The output voltage error sources include the reference voltage, error amplifier, feedback resistors, and pass element. Other sources of error on the output voltage include load regulation and line regulation. An LDOs line and load regulation measure how the voltage reference, error amplifier and pass element react to changes in line voltage and load current, respectively.

The source of load regulation inside an LDO is concentrated around the error amplifier and pass element. The reference voltage is minimally affected, if at all, to changes in load current. In contrast, the reference voltage, the error amplifier and pass fet are all affected by changes in line, which combined make up the line regulation of an LDO. Thus, the reference voltage can be thought of as dependent on the line voltage, while the offset voltage can be thought of as dependent on both the line voltage and load current.

We can write an equation to describe the error, V_E, on the output (Equation 2). The bias current flows into the resistor R_FBx. If I_BIAS+ is flowing into the error amplifier input, R_FBx = R₁ and the term I_BIASR_FBx is positive. If I_BIAS+ is flowing out of the error amplifier input, R_FBx = R₂ and the term I_BIASR_FBx is negative.

A special use case exists such that the feedback resistors are removed and the feedback pin is directly tied to V_OUT. In this case, Equation 2 can be modified to become Equation 3.