The TMP1826 and TMP1827 devices are part of the TI portfolio of high-accuracy, single-wire compatible digital output temperature sensors. The TMP182x devices simplify applications by providing a true single-wire bus-powered mode of operation, with multi-drop capability, thereby reducing the requirement for bulky cables and complex routing on space-constrained PCBs. With the dual-bus speed mode and seamless switching between the modes, the single-wire is designed for both short- and long-distance applications, enabling customers to scale their applications with minimal software updates. Because the interface is different from traditional inter-integrated circuit (I2C), universal asynchronous receiver and transmitter (UART), and serial-peripheral interfaces (SPI), this application note provides both design and software references, so that customers can implement the bus protocol on their choice of MCUs using UART, SPI, and general-purpose input/output (GPIO) peripherals. The examples provided show the TMP1826 being interfaced via different interfaces, but the same is applicable to TMP1827 devices as well.
All trademarks are the property of their respective owners.
The single-wire interface for the TMP1826, does not have a reference clock. Therefore all communication is performed asynchronously with variable pulse widths to indicate different operations. Figure 1-1 shows that the bus consists of a single pullup resistor for all devices on the bus. The devices can be powered by the supply, where the VDD pin is connected to the same supply as the host MCU and pullup resistor or bus powered, where the VDD pin is connected to GND and the device derives power from the pullup resistor.
After power up, the external pullup resistor holds the line high which is referred to as the idle state. Almost all communication is initiated by the host by driving the data line low to generate a falling edge. Based on the duration of the low period, the device interprets the data bit as a reset request, logic '0' or logic '1'.
All communication to the TMP1826 on the single-wire begins with the bus reset and response phase. The phase is initiated by the host by holding the single-wire data line low for a period of tRSTL. All devices on the bus, irrespective of their current state respond to the bus reset, by reinitializing their internal state and responding to the host-initiated bus reset. The devices respond after a minimum of tPDH, by holding the single-wire low for a time period of tRSTH as shown in Figure 1-2.