Simplify Antialiasing Filters With ADS9218

Abstract

The input of a traditional successive approximation register (SAR) analog-to-digital converter (ADC) has a switched capacitor sample and hold circuit. The process of sampling creates large transient currents (milliamps) that need to settle in a short time (nanoseconds). One of the fundamental challenges for traditional SAR applications is finding an amplifier that is capable of providing that fast-transient current to sample and hold circuit. Generally, the bandwidth of the amplifier needs to be far greater than the sampling rate requirements. The reference input for the traditional SAR ADC has a similar switched capacitor circuit, so frequently a wide bandwidth reference buffer is required. Furthermore, because the traditional SAR ADC input requires a wide bandwidth input amplifier, the output filter of the SAR ADC needs to be adjusted to a specific cutoff to eliminate transients. The selection of the filter components is a significant design challenge and the resulting filter bandwidth is generally not optimal for antialiasing and noise reduction.

The new ADS9218 SAR ADC uses an internal, wide-bandwidth, linear amplifier to drive the ADC input and reference input. The input impedance of the amplifier is in the giga-ohms, so the bandwidth requirements for the application are only limited by the required bandwidth of the signal to be converted. For example, using a traditional SAR ADC, a 1-MSPS SAR ADC typically needs an amplifier with at least 20-MHz bandwidth to respond to the input transients. Using the ADS9218, the amplifier bandwidth is only set by the signal chain frequency and distortion requirements, and does not need to respond to ADC transients because the transients are handled internally. This simplifies the design requirements and allows for many more amplifier options. Furthermore, the amplifier can be followed by a simple RC antialiasing filter, which can be tuned to the required cutoff frequency without impacting settling performance. Finally, the reference input of ADS9218 does not require any special reference buffer to achieve good reference settling as the ADC reference input has an integrated buffer.

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1 Driving Input Transients on Traditional SAR

Figure 1-1 illustrates a simplified SAR input structure for a traditional SAR ADC. The sampling process for this architecture is separated into an acquisition phase where switch S1 is closed, and a conversion phase where the switch is open and the ADC converts the sampled signal. The example covered here is a typical 2-MSPS converter with a 150-ns acquisition period and a 340-ns conversion period. During the 150-ns acquisition period the amplifier driving the input needs to respond to large transient currents. In this example, the transient is approximately 3.7 mA and must be fully settled in the 150-ns interval (see Figure 1-2).

A common amplifier used to drive the traditional SAR ADC is a 120-MHz op amp (OPA625). The discrete output filter cutoff frequency is set to 7.2 MHz (see Equation 1). To be effective, an antialiasing filter needs a cutoff frequency that is lower than the Nyquist frequency. For this device, the maximum Nyquist frequency for this ADC is 1 MHz, so clearly this does not act as an effective antialiasing filter.

Equation 1.

$f_{C} = \frac{1}{2 π R_{f i l} C_{f i l}} = \frac{1}{2 π (2.21 Ω) (10 n F)} = 7.2 M H z$

Figure 1-1 Simplified SAR Input Structure

This device also has transient current pulses on the reference input during the conversion cycle. Because of these current transients, the voltage reference requires a reference buffer. In this example design, the reference buffer is a composite two amplifier circuits so that DC performance and AC performance are optimized (see Figure 1-1). A simulation of the transient current for the ADC is shown in Figure 1-2. Notice that over the 340-ns conversion period there are 18 transient current pulses on the reference. The transient current can be as large as 42.4 mA for this device.

The main point of this section is to emphasize that the traditional SAR architecture has transients from switched capacitor circuits on the analog input and voltage reference input. These transients often require the use of wider bandwidth amplifiers than what is otherwise needed for the application. Furthermore, the transients prevent a simple antialiasing filter design.

Figure 1-2 Input and Reference Current Transients on Traditional SAR

2 Driving High-Input Impedance SAR

The ADS9218 has a high-input impedance on both the analog input and on the reference input. The device achieves this high impedance using wide bandwidth linear amplifiers. These amplifiers have giga-ohm input impedances so that external driver circuits do not have any significant loading errors. Furthermore, all the SAR switched-capacitor transients are driven by these amplifiers, so that no transients are visible at either the analog input or reference input. For this circuit, the selection of the amplifier used to drive the analog is only bounded by the desired analog performance of the signal chain. In other words, the transients do not need to be considered and the amplifier is selected based on the noise, distortion, and DC characteristics of the amplifier as needed by your application.

An example signal chain for the ADS9218 optimized for low distortion operation to 100 kHz is shown in Figure 2-1. The THS4551 is used to achieve good distortion performance for signals up to 100 kHz. Note that although the THS4551 has a 150-MHz bandwidth the THD performance begins to fall off above 100 kHz. Higher bandwidth devices consume more power, but have lower distortion at higher frequencies. Table 2-1 compares distortion, and quiescent current for three different FDA options. Note that the devices in this table are suggested for 20-kHz, 100-kHz, and 1-MHz drive options based on the distortion specifications. Also note that the table is given for a 2-V_PP signal, but the actual ADC maximum input signal is 6.4 V_PP. The increased output swing further increases distortion. The reason the table is given for 2 V_PP is that the amplifier data sheets do not all provide distortion specifications for higher output signal levels, so the table provides a comparison of the amplifiers with a common output amplitude. Figure 2-2 illustrates a typical distortion vs frequency curve from the THS4551 data sheet. Since the ADS9218 distortion is –110 dB at 2 kHz, and –101 dB at 1 MHz the amplifier is selected to achieve distortion better than the data converter at high frequency.

Figure 2-1 ADS9218 Signal Chain Optimized for Low Distortion to 100 kHz

Table 2-1 Amplifier Options for Different Maximum Frequency vs Quiescent Current

Device	Suggested Max. Freq. for low Distortion	Amplifier GBW	Output Filter Bandwidth	I_Q (mA)	HD2 Distortion at Frequency	HD3 Distortion at Frequency
THS4561	20 kHz	60 MHz	100 kHz	0.775	–128 dB at 20 kHz, 2 V_PP	–140 dB at 20 kHz, 2 V_PP
THS4551	100 kHz	150 MHz	500 kHz	1.37	–128 dB at 100 kHz, 2 V_PP	–139 dB at 100 kHz, 2 V_PP
THS4541	1 MHz	850 MHz	5 MHz	9.7	–130 dB at 1 MHz, 2 V_PP	–122 dB at 1 MHz, 2 V_PP

Figure 2-2 Distortion for THS4551 vs Input Frequency

2.1 Choosing the Antialiasing Filter

For the traditional SAR architecture, the filter at the output of a driver amplifier is used to provide a charge reservoir to help respond to the input transients. Normally the bandwidth of this filter needs to be set to a high frequency to be effective as a charge reservoir. Tuning the filter to lower frequency introduces significant distortion due to the input signal not fully settling during the acquisition period. Thus, it is generally not possible to use the charge reservoir filter as an antialiasing filter as this impacts distortion performance. Notice that the input filter on the traditional SAR (Figure 1-1) is set to 7.2 MHz which is higher than the 1-MHz Nyquist frequency. Furthermore, the process of optimizing this filter often requires parameter stepping in simulation to find the optimal RC value. This process is covered in the Driving SAR Converters video series.

The ADS9218 does not require the charge reservoir filter. Thus, the same filter structure on this device can act as an antialiasing filter. In Figure 2-1, the output filter is tuned to 500 kHz which provides some antialiasing for the 10-MHz sampling rate. Furthermore, the low cutoff frequency of this filter acts to minimize the overall intrinsic noise from the amplifier. Table 2-2 illustrates the total simulated RMS noise from the amplifier stage. Note that the highest noise is 20.4 μV for the wide bandwidth option. The ADC noise is approximately 40.2 μV, so the ADC dominates the noise and all amplifier configurations have minimal impact on SNR. The last two columns of Table 2-2 show the SNR of the amplifier and the SNR of the system. The SNR of the system ranges from 95 dB to 94 dB, so the SNR is dominated by the noise of the ADS9218. The calculations for the table are shown in Equation 2, Equation 3, and Equation 4. A detailed explanation of the noise equations is provided in the THS4551 data sheet.

Equation 2.

$E_{n} = \sqrt{{({N G e}_{n})}^{2} + 2 {(i_{n} R_{f})}^{2} + 2 N G {({4 k T R}_{f})}^{2}} \sqrt{1.57 f_{C}}$

Equation 3.

$E_{n} = \sqrt{{(2 \times 3.3 n V / \sqrt{H z})}^{2} + 2 {(0.5 p A / \sqrt{H z} \times 1 k Ω)}^{2} + 2 \times 2 \times {(3.057 n V / \sqrt{H z})}^{2}} \sqrt{1.57 \times 500 k H z} = {9.3 μ V}_{R M S}$

Equation 4.

$S N R = 20 l o g (\frac{V_{F S R_R M S}}{E_{n_R M S}}) = 20 l o g (\frac{0.707 \times 3.2 V_{p k}}{\sqrt{{(9.28 μ V)}^{2} + {(40.2 μ V)}^{2}}}) = 94.8 d B$

Table 2-2 Total Noise vs Maximum Frequency

Device	Suggested Max. Freq. for low Distortion	Output Filter Cutoff	En (nV/√Hz)	In (pA/√Hz)	Total RMS Noise of Amplifier	SNR of Amplifier for FSR of 6.4 V_PP	SNR of ADC+Amp FSR of 6.4 V_PP
THS4561	20 kHz	100 kHz	4	0.35	4.52 μV	113 dB	95.0 dB
THS4551	100 kHz	500 kHz	3.3	0.5	9.29 μV	107.7 dB	94.8 dB
THS4541	1 MHz	5 MHz	2.2	1.9	20.40 μV	100.9 dB	94.0 dB

In general, the input filter of the ADS9218 can be adjusted to any frequency to provide antialiasing and optimize noise performance whereas the traditional SAR architecture output filter is tuned to a specific frequency to facilitate settling and maintain good THD. Besides providing flexibility in the output filter design, the new topology simplifies the design process. For traditional SAR architectures, the selection of the output filter can be challenging. The Driving SAR Converters video series covers the selection of the amplifier and output filter for a traditional SAR ADC. In these types of circuits, a common approach is to choose an amplifier with a bandwidth 10 times faster than the acquisition period. Once the amplifier is selected, parameter sweep simulations are used to optimize the output filer. The result of the design process is that the amplifier bandwidth needs to be higher than is needed for the new topology. The filter is restricted to a very specific frequency which generally does not provide antialiasing and perhaps is not optimal from a noise perspective. The new topology provides the freedom to choose any amplifier and output filter that is designed for the frequency range of interest.